1/*
2 * Copyright (c) 2013, 2018-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Stan Czerniawski
38 */
39
40#include "dev/arm/smmu_v3_cmdexec.hh"
41
42#include "base/bitfield.hh"
43#include "dev/arm/smmu_v3.hh"
44
45void
46SMMUCommandExecProcess::main(Yield &yield)
47{
48    SMMUAction a;
49    a.type = ACTION_INITIAL_NOP;
50    a.pkt = NULL;
51    a.ifc = nullptr;
52    a.delay = 0;
53    yield(a);
54
55    while (true) {
56        busy = true;
57
58        while (true) {
59            // Masking depending on CMDQ_BASE.LOG2SIZE (log(number of
60            // queue entries)). Example: a value of 0b101 (32 entries)
61            // generates a 0b11111 mask.
62            int size_mask = mask(
63                smmu.regs.cmdq_base & Q_BASE_SIZE_MASK);
64
65            // In this case the wrap bit is considered (+1)
66            int size_mask_wrap = mask(
67                (smmu.regs.cmdq_base & Q_BASE_SIZE_MASK) + 1);
68
69            if ((smmu.regs.cmdq_cons & size_mask_wrap) ==
70                    (smmu.regs.cmdq_prod & size_mask_wrap))
71                break; // command queue empty
72
73            Addr cmd_addr =
74                (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) +
75                (smmu.regs.cmdq_cons & size_mask) * sizeof(SMMUCommand);
76
77            // This deliberately resets the error field in cmdq_cons!
78            smmu.regs.cmdq_cons = (smmu.regs.cmdq_cons + 1) & size_mask_wrap;
79
80            doRead(yield, cmd_addr, &cmd, sizeof(SMMUCommand));
81            smmu.processCommand(cmd);
82        }
83
84        busy = false;
85        // No more commands to process, signal the SMMU as drained
86        smmu.signalDrainDone();
87
88        doSleep(yield);
89    }
90}
91