14486SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 24486SN/A# All rights reserved. 34486SN/A# 44486SN/A# Redistribution and use in source and binary forms, with or without 54486SN/A# modification, are permitted provided that the following conditions are 64486SN/A# met: redistributions of source code must retain the above copyright 74486SN/A# notice, this list of conditions and the following disclaimer; 84486SN/A# redistributions in binary form must reproduce the above copyright 94486SN/A# notice, this list of conditions and the following disclaimer in the 104486SN/A# documentation and/or other materials provided with the distribution; 114486SN/A# neither the name of the copyright holders nor the names of its 124486SN/A# contributors may be used to endorse or promote products derived from 134486SN/A# this software without specific prior written permission. 144486SN/A# 154486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264486SN/A# 274486SN/A# Authors: Nathan Binkert 284486SN/A 293102SN/Afrom m5.SimObject import SimObject 303102SN/Afrom m5.params import * 3113665Sandreas.sandberg@arm.comfrom m5.objects.PciDevice import PciDevice 321310SN/A 331427SN/Aclass IdeID(Enum): vals = ['master', 'slave'] 341310SN/A 354982SN/Aclass IdeDisk(SimObject): 364982SN/A type = 'IdeDisk' 3711264Sandreas.sandberg@arm.com cxx_header = "dev/storage/ide_disk.hh" 384982SN/A delay = Param.Latency('1us', "Fixed disk delay in microseconds") 394982SN/A driveID = Param.IdeID('master', "Drive ID") 404982SN/A image = Param.DiskImage("Disk image") 414982SN/A 424982SN/Aclass IdeController(PciDevice): 434982SN/A type = 'IdeController' 4411264Sandreas.sandberg@arm.com cxx_header = "dev/storage/ide_ctrl.hh" 454982SN/A disks = VectorParam.IdeDisk("IDE disks attached to this controller") 464982SN/A 472916SN/A VendorID = 0x8086 482916SN/A DeviceID = 0x7111 492916SN/A Command = 0x0 502916SN/A Status = 0x280 512916SN/A Revision = 0x0 522916SN/A ClassCode = 0x01 532916SN/A SubClassCode = 0x01 542916SN/A ProgIF = 0x85 552916SN/A BAR0 = 0x00000001 562916SN/A BAR1 = 0x00000001 572916SN/A BAR2 = 0x00000001 582916SN/A BAR3 = 0x00000001 592916SN/A BAR4 = 0x00000001 602916SN/A BAR5 = 0x00000001 612916SN/A InterruptLine = 0x1f 622916SN/A InterruptPin = 0x01 632916SN/A BAR0Size = '8B' 642916SN/A BAR1Size = '4B' 652916SN/A BAR2Size = '8B' 662916SN/A BAR3Size = '4B' 672916SN/A BAR4Size = '16B' 682916SN/A 697750SN/A io_shift = Param.UInt32(0x0, "IO port shift"); 707750SN/A ctrl_offset = Param.UInt32(0x0, "IDE disk control offset") 71