1/*****************************************************************************
2 *                                McPAT/CACTI
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright 2012 Hewlett-Packard Development Company, L.P.
5 *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
6 *                          All Rights Reserved
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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31 ***************************************************************************/
32
33
34#ifndef __DECODER_H__
35#define __DECODER_H__
36
37#include <vector>
38
39#include "area.h"
40#include "component.h"
41#include "parameter.h"
42
43using namespace std;
44
45
46class Decoder : public Component {
47public:
48    Decoder(
49        int _num_dec_signals,
50        bool flag_way_select,
51        double _C_ld_dec_out,
52        double _R_wire_dec_out,
53        bool fully_assoc_,
54        bool is_dram_,
55        bool is_wl_tr_,
56        const Area & cell_);
57
58    bool   exist;
59    int    num_in_signals;
60    double C_ld_dec_out;
61    double R_wire_dec_out;
62    int    num_gates;
63    int    num_gates_min;
64    double w_dec_n[MAX_NUMBER_GATES_STAGE];
65    double w_dec_p[MAX_NUMBER_GATES_STAGE];
66    double delay;
67    //powerDef power;
68    bool   fully_assoc;
69    bool   is_dram;
70    bool   is_wl_tr;
71    const  Area & cell;
72
73
74    void   compute_widths();
75    void   compute_area();
76    double compute_delays(double inrisetime);  // return outrisetime
77
78    void leakage_feedback(double temperature);
79};
80
81
82
83class PredecBlk : public Component {
84public:
85    PredecBlk(
86        int num_dec_signals,
87        Decoder * dec,
88        double C_wire_predec_blk_out,
89        double R_wire_predec_blk_out,
90        int    num_dec_per_predec,
91        bool   is_dram_,
92        bool   is_blk1);
93
94    Decoder * dec;
95    bool exist;
96    int number_input_addr_bits;
97    double C_ld_predec_blk_out;
98    double R_wire_predec_blk_out;
99    int branch_effort_nand2_gate_output;
100    int branch_effort_nand3_gate_output;
101    bool   flag_two_unique_paths;
102    int flag_L2_gate;
103    int number_inputs_L1_gate;
104    int number_gates_L1_nand2_path;
105    int number_gates_L1_nand3_path;
106    int number_gates_L2;
107    int min_number_gates_L1;
108    int min_number_gates_L2;
109    int num_L1_active_nand2_path;
110    int num_L1_active_nand3_path;
111    double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
112    double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
113    double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
114    double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
115    double w_L2_n[MAX_NUMBER_GATES_STAGE];
116    double w_L2_p[MAX_NUMBER_GATES_STAGE];
117    double delay_nand2_path;
118    double delay_nand3_path;
119    powerDef power_nand2_path;
120    powerDef power_nand3_path;
121    powerDef power_L2;
122
123    bool is_dram_;
124
125    void compute_widths();
126    void compute_area();
127
128    void leakage_feedback(double temperature);
129
130    pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
131    // return <outrise_nand2, outrise_nand3>
132};
133
134
135class PredecBlkDrv : public Component {
136public:
137    PredecBlkDrv(
138        int   way_select,
139        PredecBlk * blk_,
140        bool  is_dram);
141
142    int flag_driver_exists;
143    int number_input_addr_bits;
144    int number_gates_nand2_path;
145    int number_gates_nand3_path;
146    int min_number_gates;
147    int num_buffers_driving_1_nand2_load;
148    int num_buffers_driving_2_nand2_load;
149    int num_buffers_driving_4_nand2_load;
150    int num_buffers_driving_2_nand3_load;
151    int num_buffers_driving_8_nand3_load;
152    int num_buffers_nand3_path;
153    double c_load_nand2_path_out;
154    double c_load_nand3_path_out;
155    double r_load_nand2_path_out;
156    double r_load_nand3_path_out;
157    double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
158    double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
159    double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
160    double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
161    double delay_nand2_path;
162    double delay_nand3_path;
163    powerDef power_nand2_path;
164    powerDef power_nand3_path;
165
166    PredecBlk * blk;
167    Decoder   * dec;
168    bool  is_dram_;
169    int   way_select;
170
171    void compute_widths();
172    void compute_area();
173
174    void leakage_feedback(double temperature);
175
176
177    pair<double, double> compute_delays(
178        double inrisetime_nand2_path,
179        double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
180
181    inline int num_addr_bits_nand2_path() {
182        return num_buffers_driving_1_nand2_load +
183               num_buffers_driving_2_nand2_load +
184               num_buffers_driving_4_nand2_load;
185    }
186    inline int num_addr_bits_nand3_path() {
187        return num_buffers_driving_2_nand3_load +
188               num_buffers_driving_8_nand3_load;
189    }
190    double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
191};
192
193
194
195class Predec : public Component {
196public:
197    Predec(
198        PredecBlkDrv * drv1,
199        PredecBlkDrv * drv2);
200
201    double compute_delays(double inrisetime);  // return outrisetime
202
203    void leakage_feedback(double temperature);
204    PredecBlk    * blk1;
205    PredecBlk    * blk2;
206    PredecBlkDrv * drv1;
207    PredecBlkDrv * drv2;
208
209    powerDef block_power;
210    powerDef driver_power;
211
212private:
213    // returns <delay, risetime>
214    pair<double, double> get_max_delay_before_decoder(
215        pair<double, double> input_pair1,
216        pair<double, double> input_pair2);
217};
218
219
220
221class Driver : public Component {
222public:
223    Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
224
225    int    number_gates;
226    int    min_number_gates;
227    double width_n[MAX_NUMBER_GATES_STAGE];
228    double width_p[MAX_NUMBER_GATES_STAGE];
229    double c_gate_load;
230    double c_wire_load;
231    double r_wire_load;
232    double delay;
233    powerDef power;
234    bool   is_dram_;
235
236    void   compute_widths();
237    double compute_delay(double inrisetime);
238};
239
240
241#endif
242