1/* 2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 * Neha Agarwal 41 */ 42 43/** 44 * @file 45 * Declaration of the trace generator that reads a trace file 46 * and plays the transactions. 47 */ 48 49#ifndef __CPU_TRAFFIC_GEN_TRACE_GEN_HH__ 50#define __CPU_TRAFFIC_GEN_TRACE_GEN_HH__ 51 52#include "base/bitfield.hh" 53#include "base/intmath.hh" 54#include "base_gen.hh" 55#include "mem/packet.hh" 56#include "proto/protoio.hh" 57 58/** 59 * The trace replay generator reads a trace file and plays 60 * back the transactions. The trace is offset with respect to 61 * the time when the state was entered. 62 */ 63class TraceGen : public BaseGen 64{ 65 66 private: 67 68 /** 69 * This struct stores a line in the trace file. 70 */ 71 struct TraceElement { 72 73 /** Specifies if the request is to be a read or a write */ 74 MemCmd cmd; 75 76 /** The address for the request */ 77 Addr addr; 78 79 /** The size of the access for the request */ 80 Addr blocksize; 81 82 /** The time at which the request should be sent */ 83 Tick tick; 84 85 /** Potential request flags to use */ 86 Request::FlagsType flags; 87 88 /** 89 * Check validity of this element. 90 * 91 * @return if this element is valid 92 */ 93 bool isValid() const { 94 return cmd != MemCmd::InvalidCmd; 95 } 96 97 /** 98 * Make this element invalid. 99 */ 100 void clear() { 101 cmd = MemCmd::InvalidCmd; 102 } 103 }; 104 105 /** 106 * The InputStream encapsulates a trace file and the 107 * internal buffers and populates TraceElements based on 108 * the input. 109 */ 110 class InputStream 111 { 112 113 private: 114 115 /// Input file stream for the protobuf trace 116 ProtoInputStream trace; 117 118 public: 119 120 /** 121 * Create a trace input stream for a given file name. 122 * 123 * @param filename Path to the file to read from 124 */ 125 InputStream(const std::string& filename); 126 127 /** 128 * Reset the stream such that it can be played once 129 * again. 130 */ 131 void reset(); 132 133 /** 134 * Check the trace header to make sure that it is of the right 135 * format. 136 */ 137 void init(); 138 139 /** 140 * Attempt to read a trace element from the stream, 141 * and also notify the caller if the end of the file 142 * was reached. 143 * 144 * @param element Trace element to populate 145 * @return True if an element could be read successfully 146 */ 147 bool read(TraceElement& element); 148 }; 149 150 public: 151 152 /** 153 * Create a trace generator. 154 * 155 * @param obj SimObject owning this sequence generator 156 * @param master_id MasterID related to the memory requests 157 * @param _duration duration of this state before transitioning 158 * @param trace_file File to read the transactions from 159 * @param addr_offset Positive offset to add to trace address 160 */ 161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration, 162 const std::string& trace_file, Addr addr_offset) 163 : BaseGen(obj, master_id, _duration), 164 trace(trace_file), 165 tickOffset(0), 166 addrOffset(addr_offset), 167 traceComplete(false) 168 { 169 } 170 171 void enter(); 172 173 PacketPtr getNextPacket(); 174 175 void exit(); 176 177 /** 178 * Returns the tick when the next request should be generated. If 179 * the end of the file has been reached, it returns MaxTick to 180 * indicate that there will be no more requests. 181 */ 182 Tick nextPacketTick(bool elastic, Tick delay) const; 183 184 private: 185 186 /** Input stream used for reading the input trace file */ 187 InputStream trace; 188 189 /** Store the current and next element in the trace */ 190 TraceElement currElement; 191 TraceElement nextElement; 192 193 /** 194 * Stores the time when the state was entered. This is to add an 195 * offset to the times stored in the trace file. This is mutable 196 * to allow us to change it as part of nextPacketTick. 197 */ 198 mutable Tick tickOffset; 199 200 /** 201 * Offset for memory requests. Used to shift the trace 202 * away from the CPU address space. 203 */ 204 Addr addrOffset; 205 206 /** 207 * Set to true when the trace replay for one instance of 208 * state is complete. 209 */ 210 bool traceComplete; 211}; 212 213#endif 214