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/gem5/src/arch/x86/
H A D	utility.cc	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/cpu/checker/
H A D	cpu_impl.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	thread_context.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	cpu.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/cpu/o3/
H A D	O3CPU.py	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	inst_queue.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	dyn_inst.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	regfile.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	thread_context.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	thread_context_impl.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	rename_impl.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	inst_queue_impl.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	cpu.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	cpu.cc	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/arch/
H A D	SConscript	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	isa_parser.py	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/arch/arm/insts/
H A D	static_inst.cc	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/arch/arm/
H A D	utility.cc	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	isa.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/cpu/
H A D	static_inst.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	simple_thread.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	thread_context.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	base_dyn_inst.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
/gem5/src/cpu/simple/
H A D	base.hh	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
H A D	base.cc	diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.

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Indexes created Thu Sep 26 06:36:22 EDT 2019