11689SN/A/* 214025Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2014, 2017-2019 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 5113449Sgabeblack@google.com#include "base/logging.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/inst_queue.hh" 548232Snate@binkert.org#include "debug/IQ.hh" 554762Snate@binkert.org#include "enums/OpClass.hh" 566221Snate@binkert.org#include "params/DerivO3CPU.hh" 574762Snate@binkert.org#include "sim/core.hh" 581060SN/A 598737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 608737Skoansin.tan@gmail.com// we open up the entire namespace std 618737Skoansin.tan@gmail.comusing std::list; 625529Snate@binkert.org 631061SN/Atemplate <class Impl> 6413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 655606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 681060SN/A{ 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 772292SN/A} 782292SN/A 792292SN/A 802292SN/Atemplate <class Impl> 812292SN/Aconst char * 825336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 832292SN/A{ 844873Sstever@eecs.umich.edu return "Functional unit completion"; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 884329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 895529Snate@binkert.org DerivO3CPUParams *params) 904329Sktlim@umich.edu : cpu(cpu_ptr), 914329Sktlim@umich.edu iewStage(iew_ptr), 924329Sktlim@umich.edu fuPool(params->fuPool), 9313561Snikos.nikoleris@arm.com iqPolicy(params->smtIQPolicy), 942292SN/A numEntries(params->numIQEntries), 952292SN/A totalWidth(params->issueWidth), 962292SN/A commitToIEWDelay(params->commitToIEWDelay) 972292SN/A{ 982292SN/A assert(fuPool); 992292SN/A 1005529Snate@binkert.org numThreads = params->numThreads; 1011060SN/A 1029920Syasuko.eckert@amd.com // Set the number of total physical registers 10312109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1049920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10612109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10713610Sgiacomo.gabrielli@arm.com params->numPhysVecPredRegs + 10812109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1091060SN/A 1101060SN/A //Create an entry for each physical register within the 1111060SN/A //dependency graph. 1122326SN/A dependGraph.resize(numPhysRegs); 1131060SN/A 1141060SN/A // Resize the register scoreboard. 1151060SN/A regScoreboard.resize(numPhysRegs); 1161060SN/A 1172292SN/A //Initialize Mem Dependence Units 11813453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1196221Snate@binkert.org memDepUnit[tid].init(params, tid); 1206221Snate@binkert.org memDepUnit[tid].setIQ(this); 1211060SN/A } 1221060SN/A 1232307SN/A resetState(); 1242292SN/A 1252292SN/A //Figure out resource sharing policy 12613561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Dynamic) { 1272292SN/A //Set Max Entries to Total ROB Capacity 1286221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1296221Snate@binkert.org maxEntries[tid] = numEntries; 1302292SN/A } 1312292SN/A 13213561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Partitioned) { 1332292SN/A //@todo:make work if part_amt doesnt divide evenly. 1342292SN/A int part_amt = numEntries / numThreads; 1352292SN/A 1362292SN/A //Divide ROB up evenly 1376221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1386221Snate@binkert.org maxEntries[tid] = part_amt; 1392292SN/A } 1402292SN/A 1412831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1422292SN/A "%i entries per thread.\n",part_amt); 14313561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Threshold) { 1442292SN/A double threshold = (double)params->smtIQThreshold / 100; 1452292SN/A 1462292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1472292SN/A 1482292SN/A //Divide up by threshold amount 1496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1506221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1512292SN/A } 1522292SN/A 1532831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1542292SN/A "%i entries per thread.\n",thresholdIQ); 1552292SN/A } 15613453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 15713453Srekai.gonzalezalberquilla@arm.com maxEntries[tid] = 0; 15813453Srekai.gonzalezalberquilla@arm.com } 1592292SN/A} 1602292SN/A 1612292SN/Atemplate <class Impl> 1622292SN/AInstructionQueue<Impl>::~InstructionQueue() 1632292SN/A{ 1642326SN/A dependGraph.reset(); 1652348SN/A#ifdef DEBUG 1662326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1672326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1682348SN/A#endif 1692292SN/A} 1702292SN/A 1712292SN/Atemplate <class Impl> 1722292SN/Astd::string 1732292SN/AInstructionQueue<Impl>::name() const 1742292SN/A{ 1752292SN/A return cpu->name() + ".iq"; 1761060SN/A} 1771060SN/A 1781061SN/Atemplate <class Impl> 1791060SN/Avoid 1801062SN/AInstructionQueue<Impl>::regStats() 1811062SN/A{ 1822301SN/A using namespace Stats; 1831062SN/A iqInstsAdded 1841062SN/A .name(name() + ".iqInstsAdded") 1851062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1861062SN/A .prereq(iqInstsAdded); 1871062SN/A 1881062SN/A iqNonSpecInstsAdded 1891062SN/A .name(name() + ".iqNonSpecInstsAdded") 1901062SN/A .desc("Number of non-speculative instructions added to the IQ") 1911062SN/A .prereq(iqNonSpecInstsAdded); 1921062SN/A 1932301SN/A iqInstsIssued 1942301SN/A .name(name() + ".iqInstsIssued") 1952301SN/A .desc("Number of instructions issued") 1962301SN/A .prereq(iqInstsIssued); 1971062SN/A 1981062SN/A iqIntInstsIssued 1991062SN/A .name(name() + ".iqIntInstsIssued") 2001062SN/A .desc("Number of integer instructions issued") 2011062SN/A .prereq(iqIntInstsIssued); 2021062SN/A 2031062SN/A iqFloatInstsIssued 2041062SN/A .name(name() + ".iqFloatInstsIssued") 2051062SN/A .desc("Number of float instructions issued") 2061062SN/A .prereq(iqFloatInstsIssued); 2071062SN/A 2081062SN/A iqBranchInstsIssued 2091062SN/A .name(name() + ".iqBranchInstsIssued") 2101062SN/A .desc("Number of branch instructions issued") 2111062SN/A .prereq(iqBranchInstsIssued); 2121062SN/A 2131062SN/A iqMemInstsIssued 2141062SN/A .name(name() + ".iqMemInstsIssued") 2151062SN/A .desc("Number of memory instructions issued") 2161062SN/A .prereq(iqMemInstsIssued); 2171062SN/A 2181062SN/A iqMiscInstsIssued 2191062SN/A .name(name() + ".iqMiscInstsIssued") 2201062SN/A .desc("Number of miscellaneous instructions issued") 2211062SN/A .prereq(iqMiscInstsIssued); 2221062SN/A 2231062SN/A iqSquashedInstsIssued 2241062SN/A .name(name() + ".iqSquashedInstsIssued") 2251062SN/A .desc("Number of squashed instructions issued") 2261062SN/A .prereq(iqSquashedInstsIssued); 2271062SN/A 2281062SN/A iqSquashedInstsExamined 2291062SN/A .name(name() + ".iqSquashedInstsExamined") 2301062SN/A .desc("Number of squashed instructions iterated over during squash;" 2311062SN/A " mainly for profiling") 2321062SN/A .prereq(iqSquashedInstsExamined); 2331062SN/A 2341062SN/A iqSquashedOperandsExamined 2351062SN/A .name(name() + ".iqSquashedOperandsExamined") 2361062SN/A .desc("Number of squashed operands that are examined and possibly " 2371062SN/A "removed from graph") 2381062SN/A .prereq(iqSquashedOperandsExamined); 2391062SN/A 2401062SN/A iqSquashedNonSpecRemoved 2411062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2421062SN/A .desc("Number of squashed non-spec instructions that were removed") 2431062SN/A .prereq(iqSquashedNonSpecRemoved); 2442361SN/A/* 2452326SN/A queueResDist 2462301SN/A .init(Num_OpClasses, 0, 99, 2) 2472301SN/A .name(name() + ".IQ:residence:") 2482301SN/A .desc("cycles from dispatch to issue") 2492301SN/A .flags(total | pdf | cdf ) 2502301SN/A ; 2512301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2522326SN/A queueResDist.subname(i, opClassStrings[i]); 2532301SN/A } 2542361SN/A*/ 2552326SN/A numIssuedDist 2562307SN/A .init(0,totalWidth,1) 2578240Snate@binkert.org .name(name() + ".issued_per_cycle") 2582301SN/A .desc("Number of insts issued each cycle") 2592307SN/A .flags(pdf) 2602301SN/A ; 2612301SN/A/* 2622301SN/A dist_unissued 2632301SN/A .init(Num_OpClasses+2) 2648240Snate@binkert.org .name(name() + ".unissued_cause") 2652301SN/A .desc("Reason ready instruction not issued") 2662301SN/A .flags(pdf | dist) 2672301SN/A ; 2682301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2692301SN/A dist_unissued.subname(i, unissued_names[i]); 2702301SN/A } 2712301SN/A*/ 2722326SN/A statIssuedInstType 2734762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2748240Snate@binkert.org .name(name() + ".FU_type") 2752301SN/A .desc("Type of FU issued") 2762301SN/A .flags(total | pdf | dist) 2772301SN/A ; 2784762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2792301SN/A 2802301SN/A // 2812301SN/A // How long did instructions for a particular FU type wait prior to issue 2822301SN/A // 2832361SN/A/* 2842326SN/A issueDelayDist 2852301SN/A .init(Num_OpClasses,0,99,2) 2868240Snate@binkert.org .name(name() + ".") 2872301SN/A .desc("cycles from operands ready to issue") 2882301SN/A .flags(pdf | cdf) 2892301SN/A ; 2902301SN/A 2912301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2922980Sgblack@eecs.umich.edu std::stringstream subname; 2932301SN/A subname << opClassStrings[i] << "_delay"; 2942326SN/A issueDelayDist.subname(i, subname.str()); 2952301SN/A } 2962361SN/A*/ 2972326SN/A issueRate 2988240Snate@binkert.org .name(name() + ".rate") 2992301SN/A .desc("Inst issue rate") 3002301SN/A .flags(total) 3012301SN/A ; 3022326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3032727Sktlim@umich.edu 3042326SN/A statFuBusy 3052301SN/A .init(Num_OpClasses) 3068240Snate@binkert.org .name(name() + ".fu_full") 3072301SN/A .desc("attempts to use FU when none available") 3082301SN/A .flags(pdf | dist) 3092301SN/A ; 3102301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3114762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3122301SN/A } 3132301SN/A 3142326SN/A fuBusy 3152301SN/A .init(numThreads) 3168240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3172301SN/A .desc("FU busy when requested") 3182301SN/A .flags(total) 3192301SN/A ; 3202301SN/A 3212326SN/A fuBusyRate 3228240Snate@binkert.org .name(name() + ".fu_busy_rate") 3232301SN/A .desc("FU busy rate (busy events/executed inst)") 3242301SN/A .flags(total) 3252301SN/A ; 3262326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3272301SN/A 3286221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3292292SN/A // Tell mem dependence unit to reg stats as well. 3306221Snate@binkert.org memDepUnit[tid].regStats(); 3312292SN/A } 3327897Shestness@cs.utexas.edu 3337897Shestness@cs.utexas.edu intInstQueueReads 3347897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3357897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3367897Shestness@cs.utexas.edu .flags(total); 3377897Shestness@cs.utexas.edu 3387897Shestness@cs.utexas.edu intInstQueueWrites 3397897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3407897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3417897Shestness@cs.utexas.edu .flags(total); 3427897Shestness@cs.utexas.edu 3437897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3447897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3457897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3467897Shestness@cs.utexas.edu .flags(total); 3477897Shestness@cs.utexas.edu 3487897Shestness@cs.utexas.edu fpInstQueueReads 3497897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3507897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3517897Shestness@cs.utexas.edu .flags(total); 3527897Shestness@cs.utexas.edu 3537897Shestness@cs.utexas.edu fpInstQueueWrites 3547897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3557897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3567897Shestness@cs.utexas.edu .flags(total); 3577897Shestness@cs.utexas.edu 35812110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3597897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3607897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3617897Shestness@cs.utexas.edu .flags(total); 3627897Shestness@cs.utexas.edu 36312319Sandreas.sandberg@arm.com vecInstQueueReads 36412319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_reads") 36512319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue reads") 36612319Sandreas.sandberg@arm.com .flags(total); 36712319Sandreas.sandberg@arm.com 36812319Sandreas.sandberg@arm.com vecInstQueueWrites 36912319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_writes") 37012319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue writes") 37112319Sandreas.sandberg@arm.com .flags(total); 37212319Sandreas.sandberg@arm.com 37312319Sandreas.sandberg@arm.com vecInstQueueWakeupAccesses 37412319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_wakeup_accesses") 37512319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue wakeup accesses") 37612319Sandreas.sandberg@arm.com .flags(total); 37712319Sandreas.sandberg@arm.com 3787897Shestness@cs.utexas.edu intAluAccesses 3797897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3807897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3817897Shestness@cs.utexas.edu .flags(total); 3827897Shestness@cs.utexas.edu 3837897Shestness@cs.utexas.edu fpAluAccesses 3847897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3857897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3867897Shestness@cs.utexas.edu .flags(total); 3877897Shestness@cs.utexas.edu 38812319Sandreas.sandberg@arm.com vecAluAccesses 38912319Sandreas.sandberg@arm.com .name(name() + ".vec_alu_accesses") 39012319Sandreas.sandberg@arm.com .desc("Number of vector alu accesses") 39112319Sandreas.sandberg@arm.com .flags(total); 39212319Sandreas.sandberg@arm.com 3931062SN/A} 3941062SN/A 3951062SN/Atemplate <class Impl> 3961062SN/Avoid 3972307SN/AInstructionQueue<Impl>::resetState() 3981060SN/A{ 3992307SN/A //Initialize thread IQ counts 40013453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 4016221Snate@binkert.org count[tid] = 0; 4026221Snate@binkert.org instList[tid].clear(); 4032307SN/A } 4041060SN/A 4052307SN/A // Initialize the number of free IQ entries. 4062307SN/A freeEntries = numEntries; 4072307SN/A 4082307SN/A // Note that in actuality, the registers corresponding to the logical 4092307SN/A // registers start off as ready. However this doesn't matter for the 4102307SN/A // IQ as the instruction should have been correctly told if those 4112307SN/A // registers are ready in rename. Thus it can all be initialized as 4122307SN/A // unready. 4132307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4142307SN/A regScoreboard[i] = false; 4152307SN/A } 4162307SN/A 41713453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 4186221Snate@binkert.org squashedSeqNum[tid] = 0; 4192307SN/A } 4202307SN/A 4212307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4222307SN/A while (!readyInsts[i].empty()) 4232307SN/A readyInsts[i].pop(); 4242307SN/A queueOnList[i] = false; 4252307SN/A readyIt[i] = listOrder.end(); 4262307SN/A } 4272307SN/A nonSpecInsts.clear(); 4282307SN/A listOrder.clear(); 4297944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 43010333Smitch.hayenga@arm.com blockedMemInsts.clear(); 43110333Smitch.hayenga@arm.com retryMemInsts.clear(); 43210511Smitch.hayenga@arm.com wbOutstanding = 0; 4331060SN/A} 4341060SN/A 4351061SN/Atemplate <class Impl> 4361060SN/Avoid 4376221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4381060SN/A{ 4392292SN/A activeThreads = at_ptr; 4402064SN/A} 4412064SN/A 4422064SN/Atemplate <class Impl> 4432064SN/Avoid 4442292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4452064SN/A{ 4464318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4471060SN/A} 4481060SN/A 4491061SN/Atemplate <class Impl> 4501060SN/Avoid 4511060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4521060SN/A{ 4531060SN/A timeBuffer = tb_ptr; 4541060SN/A 4551060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4561060SN/A} 4571060SN/A 4581684SN/Atemplate <class Impl> 45910510Smitch.hayenga@arm.combool 46010510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 46110510Smitch.hayenga@arm.com{ 46210511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 46310511Smitch.hayenga@arm.com instsToExecute.empty() && 46410511Smitch.hayenga@arm.com wbOutstanding == 0; 46510510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 46610510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 46710510Smitch.hayenga@arm.com 46810510Smitch.hayenga@arm.com return drained; 46910510Smitch.hayenga@arm.com} 47010510Smitch.hayenga@arm.com 47110510Smitch.hayenga@arm.comtemplate <class Impl> 4722307SN/Avoid 4739444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4742307SN/A{ 4759444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4769444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4779444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4789444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4792307SN/A} 4802307SN/A 4812307SN/Atemplate <class Impl> 4822307SN/Avoid 4832307SN/AInstructionQueue<Impl>::takeOverFrom() 4842307SN/A{ 4859444SAndreas.Sandberg@ARM.com resetState(); 4862307SN/A} 4872307SN/A 4882307SN/Atemplate <class Impl> 4892292SN/Aint 4906221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4912292SN/A{ 49213561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Partitioned) { 4932292SN/A return numEntries / num_threads; 4942292SN/A } else { 4952292SN/A return 0; 4962292SN/A } 4972292SN/A} 4982292SN/A 4992292SN/A 5002292SN/Atemplate <class Impl> 5012292SN/Avoid 5022292SN/AInstructionQueue<Impl>::resetEntries() 5032292SN/A{ 50413561Snikos.nikoleris@arm.com if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) { 5053867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 5062292SN/A 5076221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5086221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5092292SN/A 5103867Sbinkertn@umich.edu while (threads != end) { 5116221Snate@binkert.org ThreadID tid = *threads++; 5123867Sbinkertn@umich.edu 51313561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Partitioned) { 5143867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 51513561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Threshold && 51613561Snikos.nikoleris@arm.com active_threads == 1) { 5173867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5182292SN/A } 5192292SN/A } 5202292SN/A } 5212292SN/A} 5222292SN/A 5232292SN/Atemplate <class Impl> 5241684SN/Aunsigned 5251684SN/AInstructionQueue<Impl>::numFreeEntries() 5261684SN/A{ 5271684SN/A return freeEntries; 5281684SN/A} 5291684SN/A 5302292SN/Atemplate <class Impl> 5312292SN/Aunsigned 5326221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5332292SN/A{ 5342292SN/A return maxEntries[tid] - count[tid]; 5352292SN/A} 5362292SN/A 5371060SN/A// Might want to do something more complex if it knows how many instructions 5381060SN/A// will be issued this cycle. 5391061SN/Atemplate <class Impl> 5401060SN/Abool 5411060SN/AInstructionQueue<Impl>::isFull() 5421060SN/A{ 5431060SN/A if (freeEntries == 0) { 5441060SN/A return(true); 5451060SN/A } else { 5461060SN/A return(false); 5471060SN/A } 5481060SN/A} 5491060SN/A 5501061SN/Atemplate <class Impl> 5512292SN/Abool 5526221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5532292SN/A{ 5542292SN/A if (numFreeEntries(tid) == 0) { 5552292SN/A return(true); 5562292SN/A } else { 5572292SN/A return(false); 5582292SN/A } 5592292SN/A} 5602292SN/A 5612292SN/Atemplate <class Impl> 5622292SN/Abool 5632292SN/AInstructionQueue<Impl>::hasReadyInsts() 5642292SN/A{ 5652292SN/A if (!listOrder.empty()) { 5662292SN/A return true; 5672292SN/A } 5682292SN/A 5692292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5702292SN/A if (!readyInsts[i].empty()) { 5712292SN/A return true; 5722292SN/A } 5732292SN/A } 5742292SN/A 5752292SN/A return false; 5762292SN/A} 5772292SN/A 5782292SN/Atemplate <class Impl> 5791060SN/Avoid 58013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5811060SN/A{ 58212110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 58312110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 58412110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 58512110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 58612110SRekai.GonzalezAlberquilla@arm.com } else { 58712110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 58812110SRekai.GonzalezAlberquilla@arm.com } 5891060SN/A // Make sure the instruction is valid 5901060SN/A assert(new_inst); 5911060SN/A 59213831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Adding instruction [sn:%llu] PC %s to the IQ.\n", 5937720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5941060SN/A 5951060SN/A assert(freeEntries != 0); 5961060SN/A 5972292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5981060SN/A 5992064SN/A --freeEntries; 6001060SN/A 6012292SN/A new_inst->setInIQ(); 6021060SN/A 6031060SN/A // Look through its source registers (physical regs), and mark any 6041060SN/A // dependencies. 6051060SN/A addToDependents(new_inst); 6061060SN/A 6071060SN/A // Have this instruction set itself as the producer of its destination 6081060SN/A // register(s). 6092326SN/A addToProducers(new_inst); 6101060SN/A 6111061SN/A if (new_inst->isMemRef()) { 6122292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6131062SN/A } else { 6141062SN/A addIfReady(new_inst); 6151061SN/A } 6161061SN/A 6171062SN/A ++iqInstsAdded; 6181060SN/A 6192292SN/A count[new_inst->threadNumber]++; 6202292SN/A 6211060SN/A assert(freeEntries == (numEntries - countInsts())); 6221060SN/A} 6231060SN/A 6241061SN/Atemplate <class Impl> 6251061SN/Avoid 62613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6271061SN/A{ 6281061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6291061SN/A // to issue, then calling normal insert on the inst. 63012110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 63112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 63212110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 63312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 63412110SRekai.GonzalezAlberquilla@arm.com } else { 63512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 63612110SRekai.GonzalezAlberquilla@arm.com } 6371061SN/A 6382292SN/A assert(new_inst); 6391061SN/A 6402292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6411061SN/A 64213831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%llu] PC %s " 6432326SN/A "to the IQ.\n", 6447720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6452064SN/A 6461061SN/A assert(freeEntries != 0); 6471061SN/A 6482292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6491061SN/A 6502064SN/A --freeEntries; 6511061SN/A 6522292SN/A new_inst->setInIQ(); 6531061SN/A 6541061SN/A // Have this instruction set itself as the producer of its destination 6551061SN/A // register(s). 6562326SN/A addToProducers(new_inst); 6571061SN/A 6581061SN/A // If it's a memory instruction, add it to the memory dependency 6591061SN/A // unit. 6602292SN/A if (new_inst->isMemRef()) { 6612292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6621061SN/A } 6631062SN/A 6641062SN/A ++iqNonSpecInstsAdded; 6652292SN/A 6662292SN/A count[new_inst->threadNumber]++; 6672292SN/A 6682292SN/A assert(freeEntries == (numEntries - countInsts())); 6691061SN/A} 6701061SN/A 6711061SN/Atemplate <class Impl> 6721060SN/Avoid 67313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6741060SN/A{ 6752292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6761060SN/A 6772292SN/A insertNonSpec(barr_inst); 6782292SN/A} 6791060SN/A 6802064SN/Atemplate <class Impl> 6812333SN/Atypename Impl::DynInstPtr 6822333SN/AInstructionQueue<Impl>::getInstToExecute() 6832333SN/A{ 6842333SN/A assert(!instsToExecute.empty()); 68513429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(instsToExecute.front()); 6862333SN/A instsToExecute.pop_front(); 68712110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 6887897Shestness@cs.utexas.edu fpInstQueueReads++; 68912110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 69012110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 6917897Shestness@cs.utexas.edu } else { 6927897Shestness@cs.utexas.edu intInstQueueReads++; 6937897Shestness@cs.utexas.edu } 6942333SN/A return inst; 6952333SN/A} 6961060SN/A 6972333SN/Atemplate <class Impl> 6982064SN/Avoid 6992292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7002292SN/A{ 7012292SN/A assert(!readyInsts[op_class].empty()); 7022292SN/A 7032292SN/A ListOrderEntry queue_entry; 7042292SN/A 7052292SN/A queue_entry.queueType = op_class; 7062292SN/A 7072292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7082292SN/A 7092292SN/A ListOrderIt list_it = listOrder.begin(); 7102292SN/A ListOrderIt list_end_it = listOrder.end(); 7112292SN/A 7122292SN/A while (list_it != list_end_it) { 7132292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7142292SN/A break; 7152292SN/A } 7162292SN/A 7172292SN/A list_it++; 7181060SN/A } 7191060SN/A 7202292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7212292SN/A queueOnList[op_class] = true; 7222292SN/A} 7231060SN/A 7242292SN/Atemplate <class Impl> 7252292SN/Avoid 7262292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7272292SN/A{ 7282292SN/A // Get iterator of next item on the list 7292292SN/A // Delete the original iterator 7302292SN/A // Determine if the next item is either the end of the list or younger 7312292SN/A // than the new instruction. If so, then add in a new iterator right here. 7322292SN/A // If not, then move along. 7332292SN/A ListOrderEntry queue_entry; 7342292SN/A OpClass op_class = (*list_order_it).queueType; 7352292SN/A ListOrderIt next_it = list_order_it; 7362292SN/A 7372292SN/A ++next_it; 7382292SN/A 7392292SN/A queue_entry.queueType = op_class; 7402292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7412292SN/A 7422292SN/A while (next_it != listOrder.end() && 7432292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7442292SN/A ++next_it; 7451060SN/A } 7461060SN/A 7472292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7481060SN/A} 7491060SN/A 7502292SN/Atemplate <class Impl> 7512292SN/Avoid 75213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7532292SN/A{ 75413831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Processing FU completion [sn:%llu]\n", inst->seqNum); 7559444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7562292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7572292SN/A // long latency op). Wake it if it was. This may be overkill. 75810511Smitch.hayenga@arm.com --wbOutstanding; 7592292SN/A iewStage->wakeCPU(); 7602292SN/A 7612326SN/A if (fu_idx > -1) 7622326SN/A fuPool->freeUnitNextCycle(fu_idx); 7632292SN/A 7642326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7652326SN/A // of a cycle, otherwise they could add too many instructions to 7662326SN/A // the queue. 7675327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7682333SN/A instsToExecute.push_back(inst); 7692292SN/A} 7702292SN/A 7711061SN/A// @todo: Figure out a better way to remove the squashed items from the 7721061SN/A// lists. Checking the top item of each list to see if it's squashed 7731061SN/A// wastes time and forces jumps. 7741061SN/Atemplate <class Impl> 7751060SN/Avoid 7761060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7771060SN/A{ 7782292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7792292SN/A "the IQ.\n"); 7801060SN/A 7811060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7821060SN/A 78310333Smitch.hayenga@arm.com DynInstPtr mem_inst; 78413429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getDeferredMemInstToExecute())) { 78510333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 78610333Smitch.hayenga@arm.com } 78710333Smitch.hayenga@arm.com 78810333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 78913429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getBlockedMemInstToExecute())) { 79010333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 7917944SGiacomo.Gabrielli@arm.com } 7927944SGiacomo.Gabrielli@arm.com 7932292SN/A // Have iterator to head of the list 7942292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7952292SN/A // Try to get a FU that can do what this op needs. 7962292SN/A // If successful, change the oldestInst to the new top of the list, put 7972292SN/A // the queue in the proper place in the list. 7982292SN/A // Increment the iterator. 7992292SN/A // This will avoid trying to schedule a certain op class if there are no 8002292SN/A // FUs that handle it. 80110333Smitch.hayenga@arm.com int total_issued = 0; 8022292SN/A ListOrderIt order_it = listOrder.begin(); 8032292SN/A ListOrderIt order_end_it = listOrder.end(); 8041060SN/A 80510333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8062292SN/A OpClass op_class = (*order_it).queueType; 8071060SN/A 8082292SN/A assert(!readyInsts[op_class].empty()); 8091060SN/A 8102292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8111060SN/A 81212110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 81312110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 81412110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 81512110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 81612110SRekai.GonzalezAlberquilla@arm.com } else { 81712110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 81812110SRekai.GonzalezAlberquilla@arm.com } 8197897Shestness@cs.utexas.edu 8202292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8211060SN/A 8222292SN/A if (issuing_inst->isSquashed()) { 8232292SN/A readyInsts[op_class].pop(); 8241060SN/A 8252292SN/A if (!readyInsts[op_class].empty()) { 8262292SN/A moveToYoungerInst(order_it); 8272292SN/A } else { 8282292SN/A readyIt[op_class] = listOrder.end(); 8292292SN/A queueOnList[op_class] = false; 8301060SN/A } 8311060SN/A 8322292SN/A listOrder.erase(order_it++); 8331060SN/A 8342292SN/A ++iqSquashedInstsIssued; 8352292SN/A 8362292SN/A continue; 8371060SN/A } 8381060SN/A 83911365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8409184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8416221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8421060SN/A 8432326SN/A if (op_class != No_OpClass) { 8442326SN/A idx = fuPool->getUnit(op_class); 84512110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 84612110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 84712110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 84812110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 84912110SRekai.GonzalezAlberquilla@arm.com } else { 85012110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 85112110SRekai.GonzalezAlberquilla@arm.com } 85211365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8532326SN/A op_latency = fuPool->getOpLatency(op_class); 8541060SN/A } 8551060SN/A } 8561060SN/A 8572348SN/A // If we have an instruction that doesn't require a FU, or a 8582348SN/A // valid FU, then schedule for execution. 85911365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8609184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8612292SN/A i2e_info->size++; 8622333SN/A instsToExecute.push_back(issuing_inst); 8631060SN/A 8642326SN/A // Add the FU onto the list of FU's to be freed next 8652326SN/A // cycle if we used one. 8662326SN/A if (idx >= 0) 8672326SN/A fuPool->freeUnitNextCycle(idx); 8682292SN/A } else { 86910807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8702326SN/A // Generate completion event for the FU 87110511Smitch.hayenga@arm.com ++wbOutstanding; 8722326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8732326SN/A idx, this); 8741060SN/A 8759180Sandreas.hansson@arm.com cpu->schedule(execution, 8769180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8771060SN/A 87810807Snilay@cs.wisc.edu if (!pipelined) { 8792348SN/A // If FU isn't pipelined, then it must be freed 8802348SN/A // upon the execution completing. 8812326SN/A execution->setFreeFU(); 8822292SN/A } else { 8832292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8842326SN/A fuPool->freeUnitNextCycle(idx); 8852292SN/A } 8861060SN/A } 8871060SN/A 8887720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 88913831SAndrea.Mondelli@ucf.edu "[sn:%llu]\n", 8907720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8912292SN/A issuing_inst->seqNum); 8921060SN/A 8932292SN/A readyInsts[op_class].pop(); 8941061SN/A 8952292SN/A if (!readyInsts[op_class].empty()) { 8962292SN/A moveToYoungerInst(order_it); 8972292SN/A } else { 8982292SN/A readyIt[op_class] = listOrder.end(); 8992292SN/A queueOnList[op_class] = false; 9001060SN/A } 9011060SN/A 9022064SN/A issuing_inst->setIssued(); 9032292SN/A ++total_issued; 9042064SN/A 9058471SGiacomo.Gabrielli@arm.com#if TRACING_ON 9069046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9078471SGiacomo.Gabrielli@arm.com#endif 9088471SGiacomo.Gabrielli@arm.com 9092292SN/A if (!issuing_inst->isMemRef()) { 9102292SN/A // Memory instructions can not be freed from the IQ until they 9112292SN/A // complete. 9122292SN/A ++freeEntries; 9132301SN/A count[tid]--; 9142731Sktlim@umich.edu issuing_inst->clearInIQ(); 9152292SN/A } else { 9162301SN/A memDepUnit[tid].issue(issuing_inst); 9172292SN/A } 9182292SN/A 9192292SN/A listOrder.erase(order_it++); 9202326SN/A statIssuedInstType[tid][op_class]++; 9212292SN/A } else { 9222326SN/A statFuBusy[op_class]++; 9232326SN/A fuBusy[tid]++; 9242292SN/A ++order_it; 9251060SN/A } 9261060SN/A } 9271062SN/A 9282326SN/A numIssuedDist.sample(total_issued); 9292326SN/A iqInstsIssued+= total_issued; 9302307SN/A 9312348SN/A // If we issued any instructions, tell the CPU we had activity. 9328071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9338071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9348071SAli.Saidi@ARM.com // from the code below. 93510333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9362292SN/A cpu->activityThisCycle(); 9372292SN/A } else { 9382292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9392292SN/A } 9401060SN/A} 9411060SN/A 9421061SN/Atemplate <class Impl> 9431060SN/Avoid 9441061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9451060SN/A{ 94613831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Marking nonspeculative instruction [sn:%llu] as ready " 9472292SN/A "to execute.\n", inst); 9481062SN/A 9492292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9501060SN/A 9511061SN/A assert(inst_it != nonSpecInsts.end()); 9521060SN/A 9536221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9542292SN/A 9554033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9564033Sktlim@umich.edu 9571061SN/A (*inst_it).second->setCanIssue(); 9581060SN/A 9591062SN/A if (!(*inst_it).second->isMemRef()) { 9601062SN/A addIfReady((*inst_it).second); 9611062SN/A } else { 9622292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9631062SN/A } 9641060SN/A 9652292SN/A (*inst_it).second = NULL; 9662292SN/A 9671061SN/A nonSpecInsts.erase(inst_it); 9681060SN/A} 9691060SN/A 9701061SN/Atemplate <class Impl> 9711061SN/Avoid 9726221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9732292SN/A{ 97413831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "[tid:%i] Committing instructions older than [sn:%llu]\n", 9752292SN/A tid,inst); 9762292SN/A 9772292SN/A ListIt iq_it = instList[tid].begin(); 9782292SN/A 9792292SN/A while (iq_it != instList[tid].end() && 9802292SN/A (*iq_it)->seqNum <= inst) { 9812292SN/A ++iq_it; 9822292SN/A instList[tid].pop_front(); 9832292SN/A } 9842292SN/A 9852292SN/A assert(freeEntries == (numEntries - countInsts())); 9862292SN/A} 9872292SN/A 9882292SN/Atemplate <class Impl> 9892301SN/Aint 99013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 9911684SN/A{ 9922301SN/A int dependents = 0; 9932301SN/A 9947897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9957897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 99612110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 99712110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 99812110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 9997897Shestness@cs.utexas.edu } else { 10007897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 10017897Shestness@cs.utexas.edu } 10027897Shestness@cs.utexas.edu 10032292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10042292SN/A 10052292SN/A assert(!completed_inst->isSquashed()); 10061684SN/A 10071684SN/A // Tell the memory dependence unit to wake any dependents on this 10082292SN/A // instruction if it is a memory instruction. Also complete the memory 10092326SN/A // instruction at this point since we know it executed without issues. 10102326SN/A // @todo: Might want to rename "completeMemInst" to something that 10112326SN/A // indicates that it won't need to be replayed, and call this 10122326SN/A // earlier. Might not be a big deal. 10131684SN/A if (completed_inst->isMemRef()) { 10142292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10152292SN/A completeMemInst(completed_inst); 10162292SN/A } else if (completed_inst->isMemBarrier() || 10172292SN/A completed_inst->isWriteBarrier()) { 10182292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10191684SN/A } 10201684SN/A 10211684SN/A for (int dest_reg_idx = 0; 10221684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10231684SN/A dest_reg_idx++) 10241684SN/A { 102512105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10261684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10271684SN/A 10281684SN/A // Special case of uniq or control registers. They are not 10291684SN/A // handled by the IQ and thus have no dependency graph entry. 103012105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 103112105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 103212106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10331684SN/A continue; 10341684SN/A } 10351684SN/A 103614025Sgiacomo.gabrielli@arm.com // Avoid waking up dependents if the register is pinned 103714025Sgiacomo.gabrielli@arm.com dest_reg->decrNumPinnedWritesToComplete(); 103814025Sgiacomo.gabrielli@arm.com if (dest_reg->isPinned()) 103914025Sgiacomo.gabrielli@arm.com completed_inst->setPinnedRegsWritten(); 104014025Sgiacomo.gabrielli@arm.com 104114025Sgiacomo.gabrielli@arm.com if (dest_reg->getNumPinnedWritesToComplete() != 0) { 104214025Sgiacomo.gabrielli@arm.com DPRINTF(IQ, "Reg %d [%s] is pinned, skipping\n", 104314025Sgiacomo.gabrielli@arm.com dest_reg->index(), dest_reg->className()); 104414025Sgiacomo.gabrielli@arm.com continue; 104514025Sgiacomo.gabrielli@arm.com } 104614025Sgiacomo.gabrielli@arm.com 104712105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 104812106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 104912106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10501684SN/A 10512326SN/A //Go through the dependency chain, marking the registers as 10522326SN/A //ready within the waiting instructions. 105312106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10541684SN/A 10552326SN/A while (dep_inst) { 105613831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Waking up a dependent instruction, [sn:%llu] " 10577720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10581684SN/A 10591684SN/A // Might want to give more information to the instruction 10602326SN/A // so that it knows which of its source registers is 10612326SN/A // ready. However that would mean that the dependency 10622326SN/A // graph entries would need to hold the src_reg_idx. 10632326SN/A dep_inst->markSrcRegReady(); 10641684SN/A 10652326SN/A addIfReady(dep_inst); 10661684SN/A 106712106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10681684SN/A 10692301SN/A ++dependents; 10701684SN/A } 10711684SN/A 10722326SN/A // Reset the head node now that all of its dependents have 10732326SN/A // been woken up. 107412106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 107512106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10761684SN/A 10771684SN/A // Mark the scoreboard as having that register ready. 107812106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10791684SN/A } 10802301SN/A return dependents; 10812064SN/A} 10822064SN/A 10832064SN/Atemplate <class Impl> 10842064SN/Avoid 108513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10862064SN/A{ 10872292SN/A OpClass op_class = ready_inst->opClass(); 10882292SN/A 10892292SN/A readyInsts[op_class].push(ready_inst); 10902292SN/A 10912326SN/A // Will need to reorder the list if either a queue is not on the list, 10922326SN/A // or it has an older instruction than last time. 10932326SN/A if (!queueOnList[op_class]) { 10942326SN/A addToOrderList(op_class); 10952326SN/A } else if (readyInsts[op_class].top()->seqNum < 10962326SN/A (*readyIt[op_class]).oldestInst) { 10972326SN/A listOrder.erase(readyIt[op_class]); 10982326SN/A addToOrderList(op_class); 10992326SN/A } 11002326SN/A 11012292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 110213831SAndrea.Mondelli@ucf.edu "the ready list, PC %s opclass:%i [sn:%llu].\n", 11037720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 11042064SN/A} 11052064SN/A 11062064SN/Atemplate <class Impl> 11072064SN/Avoid 110813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 11092064SN/A{ 111013831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%llu]\n", resched_inst->seqNum); 11117944SGiacomo.Gabrielli@arm.com 11127944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 11139046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 11149046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 11157944SGiacomo.Gabrielli@arm.com 11164033Sktlim@umich.edu resched_inst->clearCanIssue(); 11172292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11182064SN/A} 11192064SN/A 11202064SN/Atemplate <class Impl> 11212064SN/Avoid 112213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11232064SN/A{ 112410333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11252292SN/A} 11262292SN/A 11272292SN/Atemplate <class Impl> 11282292SN/Avoid 112913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11302292SN/A{ 11316221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11322292SN/A 113313831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%llu]\n", 11347720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11352292SN/A 11362292SN/A ++freeEntries; 11372292SN/A 11389046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11392292SN/A 11402292SN/A memDepUnit[tid].completed(completed_inst); 11412292SN/A count[tid]--; 11421684SN/A} 11431684SN/A 11441684SN/Atemplate <class Impl> 11451684SN/Avoid 114613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11477944SGiacomo.Gabrielli@arm.com{ 11487944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11497944SGiacomo.Gabrielli@arm.com} 11507944SGiacomo.Gabrielli@arm.com 11517944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 115210333Smitch.hayenga@arm.comvoid 115313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 115410333Smitch.hayenga@arm.com{ 115510333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 115610333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 115710333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 115810333Smitch.hayenga@arm.com} 115910333Smitch.hayenga@arm.com 116010333Smitch.hayenga@arm.comtemplate <class Impl> 116110333Smitch.hayenga@arm.comvoid 116210333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 116310333Smitch.hayenga@arm.com{ 116410333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 116510333Smitch.hayenga@arm.com // Get the CPU ticking again 116610333Smitch.hayenga@arm.com cpu->wakeCPU(); 116710333Smitch.hayenga@arm.com} 116810333Smitch.hayenga@arm.com 116910333Smitch.hayenga@arm.comtemplate <class Impl> 11707944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11717944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11727944SGiacomo.Gabrielli@arm.com{ 11737944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11747944SGiacomo.Gabrielli@arm.com ++it) { 11759046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 117613429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(*it); 11777944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 117810333Smitch.hayenga@arm.com return mem_inst; 11797944SGiacomo.Gabrielli@arm.com } 11807944SGiacomo.Gabrielli@arm.com } 118110333Smitch.hayenga@arm.com return nullptr; 118210333Smitch.hayenga@arm.com} 118310333Smitch.hayenga@arm.com 118410333Smitch.hayenga@arm.comtemplate <class Impl> 118510333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 118610333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 118710333Smitch.hayenga@arm.com{ 118810333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 118910333Smitch.hayenga@arm.com return nullptr; 119010333Smitch.hayenga@arm.com } else { 119113429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(retryMemInsts.front()); 119210333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 119310333Smitch.hayenga@arm.com return mem_inst; 119410333Smitch.hayenga@arm.com } 11957944SGiacomo.Gabrielli@arm.com} 11967944SGiacomo.Gabrielli@arm.com 11977944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11987944SGiacomo.Gabrielli@arm.comvoid 119913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::violation(const DynInstPtr &store, 120013429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &faulting_load) 12011061SN/A{ 12027897Shestness@cs.utexas.edu intInstQueueWrites++; 12032292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 12041061SN/A} 12051061SN/A 12061061SN/Atemplate <class Impl> 12071060SN/Avoid 12086221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 12091060SN/A{ 121013831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "[tid:%i] Starting to squash instructions in " 12112292SN/A "the IQ.\n", tid); 12121060SN/A 12131060SN/A // Read instruction sequence number of last instruction out of the 12141060SN/A // time buffer. 12152292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12161060SN/A 121710797Sbrandon.potter@amd.com doSquash(tid); 12181061SN/A 12191061SN/A // Also tell the memory dependence unit to squash. 12202292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12211060SN/A} 12221060SN/A 12231061SN/Atemplate <class Impl> 12241061SN/Avoid 12256221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12261061SN/A{ 12272326SN/A // Start at the tail. 12282326SN/A ListIt squash_it = instList[tid].end(); 12292326SN/A --squash_it; 12301061SN/A 123113831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n", 12322292SN/A tid, squashedSeqNum[tid]); 12331061SN/A 12341061SN/A // Squash any instructions younger than the squashed sequence number 12351061SN/A // given. 12362326SN/A while (squash_it != instList[tid].end() && 12372326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12382292SN/A 12392326SN/A DynInstPtr squashed_inst = (*squash_it); 124012110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 124112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 124212110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 124312110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 124412110SRekai.GonzalezAlberquilla@arm.com } else { 124512110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 124612110SRekai.GonzalezAlberquilla@arm.com } 12471061SN/A 12481061SN/A // Only handle the instruction if it actually is in the IQ and 12491061SN/A // hasn't already been squashed in the IQ. 12502292SN/A if (squashed_inst->threadNumber != tid || 12512292SN/A squashed_inst->isSquashedInIQ()) { 12522326SN/A --squash_it; 12532292SN/A continue; 12542292SN/A } 12552292SN/A 12562292SN/A if (!squashed_inst->isIssued() || 12572292SN/A (squashed_inst->isMemRef() && 12589046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12591062SN/A 126013831SAndrea.Mondelli@ucf.edu DPRINTF(IQ, "[tid:%i] Instruction [sn:%llu] PC %s squashed.\n", 12617720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12622367SN/A 126310032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 126410032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 126513652Sqtt2@cornell.edu (squashed_inst->isStore() && 126610032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 126710032SGiacomo.Gabrielli@arm.com 12681061SN/A // Remove the instruction from the dependency list. 126910032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 127010032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 127110032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 127213652Sqtt2@cornell.edu !squashed_inst->isAtomic() && 127310032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 127410032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12751061SN/A 12761061SN/A for (int src_reg_idx = 0; 12771681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12781061SN/A src_reg_idx++) 12791061SN/A { 128012105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12811061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12821061SN/A 12832326SN/A // Only remove it from the dependency graph if it 12842326SN/A // was placed there in the first place. 12852326SN/A 12862326SN/A // Instead of doing a linked list traversal, we 12872326SN/A // can just remove these squashed instructions 12882326SN/A // either at issue time, or when the register is 12892326SN/A // overwritten. The only downside to this is it 12902326SN/A // leaves more room for error. 12912292SN/A 12921061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 129312105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 129412106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 129512106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12961061SN/A } 12971062SN/A 12981062SN/A ++iqSquashedOperandsExamined; 12991061SN/A } 130013590Srekai.gonzalezalberquilla@arm.com 13014033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 13024033Sktlim@umich.edu !squashed_inst->isCompleted()) { 13032292SN/A NonSpecMapIt ns_inst_it = 13042292SN/A nonSpecInsts.find(squashed_inst->seqNum); 13058275SAli.Saidi@ARM.com 130610017Sandreas.hansson@arm.com // we remove non-speculative instructions from 130710017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 130810017Sandreas.hansson@arm.com // cannot always expect to find them 13094033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 131010017Sandreas.hansson@arm.com // loads that became ready but stalled on a 131110017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 131210017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 131310017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 131410017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 13154033Sktlim@umich.edu } else { 13161062SN/A 13174033Sktlim@umich.edu (*ns_inst_it).second = NULL; 13181681SN/A 13194033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 13201062SN/A 13214033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13224033Sktlim@umich.edu } 13231061SN/A } 13241061SN/A 13251061SN/A // Might want to also clear out the head of the dependency graph. 13261061SN/A 13271061SN/A // Mark it as squashed within the IQ. 13281061SN/A squashed_inst->setSquashedInIQ(); 13291061SN/A 13302292SN/A // @todo: Remove this hack where several statuses are set so the 13312292SN/A // inst will flow through the rest of the pipeline. 13321681SN/A squashed_inst->setIssued(); 13331681SN/A squashed_inst->setCanCommit(); 13342731Sktlim@umich.edu squashed_inst->clearInIQ(); 13352292SN/A 13362292SN/A //Update Thread IQ Count 13372292SN/A count[squashed_inst->threadNumber]--; 13381681SN/A 13391681SN/A ++freeEntries; 13401061SN/A } 13411061SN/A 134212833Sjang.hanhwi@gmail.com // IQ clears out the heads of the dependency graph only when 134312833Sjang.hanhwi@gmail.com // instructions reach writeback stage. If an instruction is squashed 134412833Sjang.hanhwi@gmail.com // before writeback stage, its head of dependency graph would not be 134512833Sjang.hanhwi@gmail.com // cleared out; it holds the instruction's DynInstPtr. This prevents 134612833Sjang.hanhwi@gmail.com // freeing the squashed instruction's DynInst. 134712833Sjang.hanhwi@gmail.com // Thus, we need to manually clear out the squashed instructions' heads 134812833Sjang.hanhwi@gmail.com // of dependency graph. 134912833Sjang.hanhwi@gmail.com for (int dest_reg_idx = 0; 135012833Sjang.hanhwi@gmail.com dest_reg_idx < squashed_inst->numDestRegs(); 135112833Sjang.hanhwi@gmail.com dest_reg_idx++) 135212833Sjang.hanhwi@gmail.com { 135312833Sjang.hanhwi@gmail.com PhysRegIdPtr dest_reg = 135412833Sjang.hanhwi@gmail.com squashed_inst->renamedDestRegIdx(dest_reg_idx); 135512833Sjang.hanhwi@gmail.com if (dest_reg->isFixedMapping()){ 135612833Sjang.hanhwi@gmail.com continue; 135712833Sjang.hanhwi@gmail.com } 135812833Sjang.hanhwi@gmail.com assert(dependGraph.empty(dest_reg->flatIndex())); 135912833Sjang.hanhwi@gmail.com dependGraph.clearInst(dest_reg->flatIndex()); 136012833Sjang.hanhwi@gmail.com } 13612326SN/A instList[tid].erase(squash_it--); 13621062SN/A ++iqSquashedInstsExamined; 13631061SN/A } 13641060SN/A} 13651060SN/A 13661061SN/Atemplate <class Impl> 13671060SN/Abool 136813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13691060SN/A{ 13701060SN/A // Loop through the instruction's source registers, adding 13711060SN/A // them to the dependency list if they are not ready. 13721060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13731060SN/A bool return_val = false; 13741060SN/A 13751060SN/A for (int src_reg_idx = 0; 13761060SN/A src_reg_idx < total_src_regs; 13771060SN/A src_reg_idx++) 13781060SN/A { 13791060SN/A // Only add it to the dependency graph if it's not ready. 13801060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 138112105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13821060SN/A 13831060SN/A // Check the IQ's scoreboard to make sure the register 13841060SN/A // hasn't become ready while the instruction was in flight 13851060SN/A // between stages. Only if it really isn't ready should 13861060SN/A // it be added to the dependency graph. 138712105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13881061SN/A continue; 138912106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 139012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13911060SN/A "is being added to the dependency chain.\n", 139212106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 139312106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13941060SN/A 139512106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13961060SN/A 13971060SN/A // Change the return value to indicate that something 13981060SN/A // was added to the dependency graph. 13991060SN/A return_val = true; 14001060SN/A } else { 140112105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 14021060SN/A "became ready before it reached the IQ.\n", 140312106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 140412106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 14051060SN/A // Mark a register ready within the instruction. 14062326SN/A new_inst->markSrcRegReady(src_reg_idx); 14071060SN/A } 14081060SN/A } 14091060SN/A } 14101060SN/A 14111060SN/A return return_val; 14121060SN/A} 14131060SN/A 14141061SN/Atemplate <class Impl> 14151060SN/Avoid 141613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14171060SN/A{ 14182326SN/A // Nothing really needs to be marked when an instruction becomes 14192326SN/A // the producer of a register's value, but for convenience a ptr 14202326SN/A // to the producing instruction will be placed in the head node of 14212326SN/A // the dependency links. 14221060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14231060SN/A 14241060SN/A for (int dest_reg_idx = 0; 14251060SN/A dest_reg_idx < total_dest_regs; 14261060SN/A dest_reg_idx++) 14271060SN/A { 142812105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14291061SN/A 143012105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 14311061SN/A // dependencies as these instructions must be executed at commit. 143212105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 14331061SN/A continue; 14341060SN/A } 14351060SN/A 143612106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 14372326SN/A dependGraph.dump(); 143812105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 143912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 144012106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14412064SN/A } 14421062SN/A 144312106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14441062SN/A 14451060SN/A // Mark the scoreboard to say it's not yet ready. 144612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14471060SN/A } 14481060SN/A} 14491060SN/A 14501061SN/Atemplate <class Impl> 14511060SN/Avoid 145213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14531060SN/A{ 14542326SN/A // If the instruction now has all of its source registers 14551060SN/A // available, then add it to the list of ready instructions. 14561060SN/A if (inst->readyToIssue()) { 14571061SN/A 14581060SN/A //Add the instruction to the proper ready list. 14592292SN/A if (inst->isMemRef()) { 14601061SN/A 14612292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14621061SN/A 14631062SN/A // Message to the mem dependence unit that this instruction has 14641062SN/A // its registers ready. 14652292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14661062SN/A 14672292SN/A return; 14682292SN/A } 14691062SN/A 14702292SN/A OpClass op_class = inst->opClass(); 14711061SN/A 14722292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 147313831SAndrea.Mondelli@ucf.edu "the ready list, PC %s opclass:%i [sn:%llu].\n", 14747720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14751061SN/A 14762292SN/A readyInsts[op_class].push(inst); 14771061SN/A 14782326SN/A // Will need to reorder the list if either a queue is not on the list, 14792326SN/A // or it has an older instruction than last time. 14802326SN/A if (!queueOnList[op_class]) { 14812326SN/A addToOrderList(op_class); 14822326SN/A } else if (readyInsts[op_class].top()->seqNum < 14832326SN/A (*readyIt[op_class]).oldestInst) { 14842326SN/A listOrder.erase(readyIt[op_class]); 14852326SN/A addToOrderList(op_class); 14861060SN/A } 14871060SN/A } 14881060SN/A} 14891060SN/A 14901061SN/Atemplate <class Impl> 14911061SN/Aint 14921061SN/AInstructionQueue<Impl>::countInsts() 14931061SN/A{ 14942292SN/A return numEntries - freeEntries; 14951681SN/A} 14961681SN/A 14971681SN/Atemplate <class Impl> 14981681SN/Avoid 14991061SN/AInstructionQueue<Impl>::dumpLists() 15001061SN/A{ 15012292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15022292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15031061SN/A 15042292SN/A cprintf("\n"); 15052292SN/A } 15061061SN/A 15071061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15081061SN/A 15092292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15102292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15111061SN/A 15121061SN/A cprintf("Non speculative list: "); 15131061SN/A 15142292SN/A while (non_spec_it != non_spec_end_it) { 151513831SAndrea.Mondelli@ucf.edu cprintf("%s [sn:%llu]", (*non_spec_it).second->pcState(), 15162292SN/A (*non_spec_it).second->seqNum); 15171061SN/A ++non_spec_it; 15181061SN/A } 15191061SN/A 15201061SN/A cprintf("\n"); 15211061SN/A 15222292SN/A ListOrderIt list_order_it = listOrder.begin(); 15232292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15242292SN/A int i = 1; 15252292SN/A 15262292SN/A cprintf("List order: "); 15272292SN/A 15282292SN/A while (list_order_it != list_order_end_it) { 152913831SAndrea.Mondelli@ucf.edu cprintf("%i OpClass:%i [sn:%llu] ", i, (*list_order_it).queueType, 15302292SN/A (*list_order_it).oldestInst); 15312292SN/A 15322292SN/A ++list_order_it; 15332292SN/A ++i; 15342292SN/A } 15352292SN/A 15362292SN/A cprintf("\n"); 15371061SN/A} 15382292SN/A 15392292SN/A 15402292SN/Atemplate <class Impl> 15412292SN/Avoid 15422292SN/AInstructionQueue<Impl>::dumpInsts() 15432292SN/A{ 15446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15452292SN/A int num = 0; 15462292SN/A int valid_num = 0; 15476221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15482292SN/A 15496221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15506221Snate@binkert.org cprintf("Instruction:%i\n", num); 15512292SN/A if (!(*inst_list_it)->isSquashed()) { 15522292SN/A if (!(*inst_list_it)->isIssued()) { 15532292SN/A ++valid_num; 15542292SN/A cprintf("Count:%i\n", valid_num); 15552292SN/A } else if ((*inst_list_it)->isMemRef() && 15569046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15572326SN/A // Loads that have not been marked as executed 15582326SN/A // still count towards the total instructions. 15592292SN/A ++valid_num; 15602292SN/A cprintf("Count:%i\n", valid_num); 15612292SN/A } 15622292SN/A } 15632292SN/A 156413831SAndrea.Mondelli@ucf.edu cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" 15652292SN/A "Issued:%i\nSquashed:%i\n", 15667720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15672292SN/A (*inst_list_it)->seqNum, 15682292SN/A (*inst_list_it)->threadNumber, 15692292SN/A (*inst_list_it)->isIssued(), 15702292SN/A (*inst_list_it)->isSquashed()); 15712292SN/A 15722292SN/A if ((*inst_list_it)->isMemRef()) { 15739046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15742292SN/A } 15752292SN/A 15762292SN/A cprintf("\n"); 15772292SN/A 15782292SN/A inst_list_it++; 15792292SN/A ++num; 15802292SN/A } 15812292SN/A } 15822348SN/A 15832348SN/A cprintf("Insts to Execute list:\n"); 15842348SN/A 15852348SN/A int num = 0; 15862348SN/A int valid_num = 0; 15872348SN/A ListIt inst_list_it = instsToExecute.begin(); 15882348SN/A 15892348SN/A while (inst_list_it != instsToExecute.end()) 15902348SN/A { 15912348SN/A cprintf("Instruction:%i\n", 15922348SN/A num); 15932348SN/A if (!(*inst_list_it)->isSquashed()) { 15942348SN/A if (!(*inst_list_it)->isIssued()) { 15952348SN/A ++valid_num; 15962348SN/A cprintf("Count:%i\n", valid_num); 15972348SN/A } else if ((*inst_list_it)->isMemRef() && 15989046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15992348SN/A // Loads that have not been marked as executed 16002348SN/A // still count towards the total instructions. 16012348SN/A ++valid_num; 16022348SN/A cprintf("Count:%i\n", valid_num); 16032348SN/A } 16042348SN/A } 16052348SN/A 160613831SAndrea.Mondelli@ucf.edu cprintf("PC: %s\n[sn:%llu]\n[tid:%i]\n" 16072348SN/A "Issued:%i\nSquashed:%i\n", 16087720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 16092348SN/A (*inst_list_it)->seqNum, 16102348SN/A (*inst_list_it)->threadNumber, 16112348SN/A (*inst_list_it)->isIssued(), 16122348SN/A (*inst_list_it)->isSquashed()); 16132348SN/A 16142348SN/A if ((*inst_list_it)->isMemRef()) { 16159046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16162348SN/A } 16172348SN/A 16182348SN/A cprintf("\n"); 16192348SN/A 16202348SN/A inst_list_it++; 16212348SN/A ++num; 16222348SN/A } 16232292SN/A} 16249944Smatt.horsnell@ARM.com 16259944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1626