Searched hist:12104 (Results 26 - 50 of 68) sorted by relevance
| /gem5/src/arch/x86/insts/ | ||
| H A D | static_inst.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | limmop.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/alpha/isa/ | ||
| H A D | fp.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | branch.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/power/insts/ | ||
| H A D | static_inst.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/arm/insts/ | ||
| H A D | macromem.cc | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | mem.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | misc.cc | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/mips/ | ||
| H A D | registers.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | mt.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/x86/ | ||
| H A D | registers.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/cpu/o3/probe/ | ||
| H A D | elastic_trace.cc | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/cpu/o3/ | ||
| H A D | rename_map.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | rob.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | rename_map.cc | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/mips/isa/formats/ | ||
| H A D | mt.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | int.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/generic/ | ||
| H A D | types.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/sparc/isa/formats/ | ||
| H A D | integerop.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| H A D | priv.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/mips/isa/ | ||
| H A D | base.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/riscv/ | ||
| H A D | registers.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/arm/ | ||
| H A D | registers.hh | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/sparc/isa/ | ||
| H A D | base.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
| /gem5/src/arch/sparc/isa/formats/mem/ | ||
| H A D | util.isa | diff 12104:edd63f9c6184 Wed Apr 05 01:46:00 EDT 2017 Nathanael Premillieu <nathanael.premillieu@arm.com> arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700 |
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