17118Sgblack@eecs.umich.edu/* 27118Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37118Sgblack@eecs.umich.edu * All rights reserved 47118Sgblack@eecs.umich.edu * 57118Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67118Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77118Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87118Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97118Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107118Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117118Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127118Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137118Sgblack@eecs.umich.edu * 147118Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 466253Sgblack@eecs.umich.edu 476253Sgblack@eecs.umich.edunamespace ArmISA 486253Sgblack@eecs.umich.edu{ 497118Sgblack@eecs.umich.edu 507720Sgblack@eecs.umich.educlass MightBeMicro : public PredOp 517720Sgblack@eecs.umich.edu{ 527720Sgblack@eecs.umich.edu protected: 537720Sgblack@eecs.umich.edu MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 547720Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass) 557720Sgblack@eecs.umich.edu {} 567720Sgblack@eecs.umich.edu 577720Sgblack@eecs.umich.edu void 587720Sgblack@eecs.umich.edu advancePC(PCState &pcState) const 597720Sgblack@eecs.umich.edu { 607720Sgblack@eecs.umich.edu if (flags[IsLastMicroop]) { 617720Sgblack@eecs.umich.edu pcState.uEnd(); 627720Sgblack@eecs.umich.edu } else if (flags[IsMicroop]) { 637720Sgblack@eecs.umich.edu pcState.uAdvance(); 647720Sgblack@eecs.umich.edu } else { 657720Sgblack@eecs.umich.edu pcState.advance(); 667720Sgblack@eecs.umich.edu } 677720Sgblack@eecs.umich.edu } 687720Sgblack@eecs.umich.edu}; 697720Sgblack@eecs.umich.edu 707291Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 717720Sgblack@eecs.umich.educlass RfeOp : public MightBeMicro 727291Sgblack@eecs.umich.edu{ 737291Sgblack@eecs.umich.edu public: 747291Sgblack@eecs.umich.edu enum AddrMode { 757291Sgblack@eecs.umich.edu DecrementAfter, 767291Sgblack@eecs.umich.edu DecrementBefore, 777291Sgblack@eecs.umich.edu IncrementAfter, 787291Sgblack@eecs.umich.edu IncrementBefore 797291Sgblack@eecs.umich.edu }; 807291Sgblack@eecs.umich.edu protected: 817291Sgblack@eecs.umich.edu IntRegIndex base; 827291Sgblack@eecs.umich.edu AddrMode mode; 837291Sgblack@eecs.umich.edu bool wb; 848140SMatt.Horsnell@arm.com IntRegIndex ura, urb, urc; 858140SMatt.Horsnell@arm.com static const unsigned numMicroops = 3; 867646Sgene.wu@arm.com 877646Sgene.wu@arm.com StaticInstPtr *uops; 887291Sgblack@eecs.umich.edu 897291Sgblack@eecs.umich.edu RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 907291Sgblack@eecs.umich.edu IntRegIndex _base, AddrMode _mode, bool _wb) 917720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 928140SMatt.Horsnell@arm.com base(_base), mode(_mode), wb(_wb), 938140SMatt.Horsnell@arm.com ura(INTREG_UREG0), urb(INTREG_UREG1), 948140SMatt.Horsnell@arm.com urc(INTREG_UREG2), 958140SMatt.Horsnell@arm.com uops(NULL) 967291Sgblack@eecs.umich.edu {} 977291Sgblack@eecs.umich.edu 987646Sgene.wu@arm.com virtual 997646Sgene.wu@arm.com ~RfeOp() 1007646Sgene.wu@arm.com { 1017747SAli.Saidi@ARM.com delete [] uops; 1027646Sgene.wu@arm.com } 1037646Sgene.wu@arm.com 1047646Sgene.wu@arm.com StaticInstPtr 10512616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 1067646Sgene.wu@arm.com { 1077646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 1087646Sgene.wu@arm.com return uops[microPC]; 1097646Sgene.wu@arm.com } 1107646Sgene.wu@arm.com 11112616Sgabeblack@google.com std::string generateDisassembly( 11212616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 1137291Sgblack@eecs.umich.edu}; 1147291Sgblack@eecs.umich.edu 1157312Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 1167720Sgblack@eecs.umich.educlass SrsOp : public MightBeMicro 1177312Sgblack@eecs.umich.edu{ 1187312Sgblack@eecs.umich.edu public: 1197312Sgblack@eecs.umich.edu enum AddrMode { 1207312Sgblack@eecs.umich.edu DecrementAfter, 1217312Sgblack@eecs.umich.edu DecrementBefore, 1227312Sgblack@eecs.umich.edu IncrementAfter, 1237312Sgblack@eecs.umich.edu IncrementBefore 1247312Sgblack@eecs.umich.edu }; 1257312Sgblack@eecs.umich.edu protected: 1267312Sgblack@eecs.umich.edu uint32_t regMode; 1277312Sgblack@eecs.umich.edu AddrMode mode; 1287312Sgblack@eecs.umich.edu bool wb; 1297646Sgene.wu@arm.com static const unsigned numMicroops = 2; 1307646Sgene.wu@arm.com 1317646Sgene.wu@arm.com StaticInstPtr *uops; 1327312Sgblack@eecs.umich.edu 1337312Sgblack@eecs.umich.edu SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1347312Sgblack@eecs.umich.edu uint32_t _regMode, AddrMode _mode, bool _wb) 1357720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 1367646Sgene.wu@arm.com regMode(_regMode), mode(_mode), wb(_wb), uops(NULL) 1377312Sgblack@eecs.umich.edu {} 1387312Sgblack@eecs.umich.edu 1397646Sgene.wu@arm.com virtual 1407646Sgene.wu@arm.com ~SrsOp() 1417646Sgene.wu@arm.com { 1427845SAli.Saidi@ARM.com delete [] uops; 1437646Sgene.wu@arm.com } 1447646Sgene.wu@arm.com 1457646Sgene.wu@arm.com StaticInstPtr 14612616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 1477646Sgene.wu@arm.com { 1487646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 1497646Sgene.wu@arm.com return uops[microPC]; 1507646Sgene.wu@arm.com } 1517646Sgene.wu@arm.com 15212616Sgabeblack@google.com std::string generateDisassembly( 15312616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 1547312Sgblack@eecs.umich.edu}; 1557312Sgblack@eecs.umich.edu 1567720Sgblack@eecs.umich.educlass Memory : public MightBeMicro 1577118Sgblack@eecs.umich.edu{ 1587118Sgblack@eecs.umich.edu public: 1597118Sgblack@eecs.umich.edu enum AddrMode { 1607118Sgblack@eecs.umich.edu AddrMd_Offset, 1617118Sgblack@eecs.umich.edu AddrMd_PreIndex, 1627118Sgblack@eecs.umich.edu AddrMd_PostIndex 1637118Sgblack@eecs.umich.edu }; 1647118Sgblack@eecs.umich.edu 1657118Sgblack@eecs.umich.edu protected: 1667118Sgblack@eecs.umich.edu 1677118Sgblack@eecs.umich.edu IntRegIndex dest; 1687118Sgblack@eecs.umich.edu IntRegIndex base; 1697118Sgblack@eecs.umich.edu bool add; 1707646Sgene.wu@arm.com static const unsigned numMicroops = 3; 1717646Sgene.wu@arm.com 1727646Sgene.wu@arm.com StaticInstPtr *uops; 1737118Sgblack@eecs.umich.edu 1747132Sgblack@eecs.umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1757132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add) 1767720Sgblack@eecs.umich.edu : MightBeMicro(mnem, _machInst, __opClass), 1777646Sgene.wu@arm.com dest(_dest), base(_base), add(_add), uops(NULL) 1787118Sgblack@eecs.umich.edu {} 1797118Sgblack@eecs.umich.edu 1807646Sgene.wu@arm.com virtual 1817646Sgene.wu@arm.com ~Memory() 1827646Sgene.wu@arm.com { 1837646Sgene.wu@arm.com delete [] uops; 1847646Sgene.wu@arm.com } 1857646Sgene.wu@arm.com 1867646Sgene.wu@arm.com StaticInstPtr 18712616Sgabeblack@google.com fetchMicroop(MicroPC microPC) const override 1887646Sgene.wu@arm.com { 1897646Sgene.wu@arm.com assert(uops != NULL && microPC < numMicroops); 1907646Sgene.wu@arm.com return uops[microPC]; 1917646Sgene.wu@arm.com } 1927646Sgene.wu@arm.com 1937118Sgblack@eecs.umich.edu virtual void 1947118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 1957118Sgblack@eecs.umich.edu {} 1967118Sgblack@eecs.umich.edu 1977279Sgblack@eecs.umich.edu virtual void 1987279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 1997279Sgblack@eecs.umich.edu { 20012104Snathanael.premillieu@arm.com printIntReg(os, dest); 2017279Sgblack@eecs.umich.edu } 2027279Sgblack@eecs.umich.edu 2037118Sgblack@eecs.umich.edu void printInst(std::ostream &os, AddrMode addrMode) const; 2047118Sgblack@eecs.umich.edu}; 2057118Sgblack@eecs.umich.edu 2067118Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 2077132Sgblack@eecs.umich.educlass MemoryImm : public Memory 2087118Sgblack@eecs.umich.edu{ 2097118Sgblack@eecs.umich.edu protected: 2107118Sgblack@eecs.umich.edu int32_t imm; 2117118Sgblack@eecs.umich.edu 2127132Sgblack@eecs.umich.edu MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2137132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 2147132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 2157118Sgblack@eecs.umich.edu {} 2167118Sgblack@eecs.umich.edu 2177118Sgblack@eecs.umich.edu void 2187118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2197118Sgblack@eecs.umich.edu { 2207118Sgblack@eecs.umich.edu int32_t pImm = imm; 2217118Sgblack@eecs.umich.edu if (!add) 2227118Sgblack@eecs.umich.edu pImm = -pImm; 2237118Sgblack@eecs.umich.edu ccprintf(os, "#%d", pImm); 2247118Sgblack@eecs.umich.edu } 2257118Sgblack@eecs.umich.edu}; 2267118Sgblack@eecs.umich.edu 2277303Sgblack@eecs.umich.educlass MemoryExImm : public MemoryImm 2287303Sgblack@eecs.umich.edu{ 2297303Sgblack@eecs.umich.edu protected: 2307303Sgblack@eecs.umich.edu IntRegIndex result; 2317303Sgblack@eecs.umich.edu 2327303Sgblack@eecs.umich.edu MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2337303Sgblack@eecs.umich.edu IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base, 2347303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 2357303Sgblack@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2367303Sgblack@eecs.umich.edu result(_result) 2377303Sgblack@eecs.umich.edu {} 2387303Sgblack@eecs.umich.edu 2397303Sgblack@eecs.umich.edu void 2407303Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2417303Sgblack@eecs.umich.edu { 24212104Snathanael.premillieu@arm.com printIntReg(os, result); 2437303Sgblack@eecs.umich.edu os << ", "; 2447303Sgblack@eecs.umich.edu MemoryImm::printDest(os); 2457303Sgblack@eecs.umich.edu } 2467303Sgblack@eecs.umich.edu}; 2477303Sgblack@eecs.umich.edu 2487279Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 2497279Sgblack@eecs.umich.educlass MemoryDImm : public MemoryImm 2507279Sgblack@eecs.umich.edu{ 2517279Sgblack@eecs.umich.edu protected: 2527279Sgblack@eecs.umich.edu IntRegIndex dest2; 2537279Sgblack@eecs.umich.edu 2547279Sgblack@eecs.umich.edu MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2557279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 2567279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 2577279Sgblack@eecs.umich.edu : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 2587279Sgblack@eecs.umich.edu dest2(_dest2) 2597279Sgblack@eecs.umich.edu {} 2607279Sgblack@eecs.umich.edu 2617279Sgblack@eecs.umich.edu void 2627279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2637279Sgblack@eecs.umich.edu { 2647279Sgblack@eecs.umich.edu MemoryImm::printDest(os); 2657279Sgblack@eecs.umich.edu os << ", "; 26612104Snathanael.premillieu@arm.com printIntReg(os, dest2); 2677279Sgblack@eecs.umich.edu } 2687279Sgblack@eecs.umich.edu}; 2697279Sgblack@eecs.umich.edu 2707303Sgblack@eecs.umich.educlass MemoryExDImm : public MemoryDImm 2717303Sgblack@eecs.umich.edu{ 2727303Sgblack@eecs.umich.edu protected: 2737303Sgblack@eecs.umich.edu IntRegIndex result; 2747303Sgblack@eecs.umich.edu 2757303Sgblack@eecs.umich.edu MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2767303Sgblack@eecs.umich.edu IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, 2777303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 2787303Sgblack@eecs.umich.edu : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2, 2797303Sgblack@eecs.umich.edu _base, _add, _imm), result(_result) 2807303Sgblack@eecs.umich.edu {} 2817303Sgblack@eecs.umich.edu 2827303Sgblack@eecs.umich.edu void 2837303Sgblack@eecs.umich.edu printDest(std::ostream &os) const 2847303Sgblack@eecs.umich.edu { 28512104Snathanael.premillieu@arm.com printIntReg(os, result); 2867303Sgblack@eecs.umich.edu os << ", "; 2877303Sgblack@eecs.umich.edu MemoryDImm::printDest(os); 2887303Sgblack@eecs.umich.edu } 2897303Sgblack@eecs.umich.edu}; 2907303Sgblack@eecs.umich.edu 2917118Sgblack@eecs.umich.edu// The address is a shifted register plus an immediate 2927132Sgblack@eecs.umich.educlass MemoryReg : public Memory 2937118Sgblack@eecs.umich.edu{ 2947118Sgblack@eecs.umich.edu protected: 2957118Sgblack@eecs.umich.edu int32_t shiftAmt; 2967118Sgblack@eecs.umich.edu ArmShiftType shiftType; 2977118Sgblack@eecs.umich.edu IntRegIndex index; 2987118Sgblack@eecs.umich.edu 2997132Sgblack@eecs.umich.edu MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 3007132Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, 3017132Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3027132Sgblack@eecs.umich.edu IntRegIndex _index) 3037132Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _dest, _base, _add), 3047118Sgblack@eecs.umich.edu shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 3057118Sgblack@eecs.umich.edu {} 3067118Sgblack@eecs.umich.edu 3077428Sgblack@eecs.umich.edu void printOffset(std::ostream &os) const; 3087118Sgblack@eecs.umich.edu}; 3097118Sgblack@eecs.umich.edu 3107279Sgblack@eecs.umich.educlass MemoryDReg : public MemoryReg 3117279Sgblack@eecs.umich.edu{ 3127279Sgblack@eecs.umich.edu protected: 3137279Sgblack@eecs.umich.edu IntRegIndex dest2; 3147279Sgblack@eecs.umich.edu 3157279Sgblack@eecs.umich.edu MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 3167279Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 3177279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3187279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3197279Sgblack@eecs.umich.edu IntRegIndex _index) 3207279Sgblack@eecs.umich.edu : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add, 3217279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index), 3227279Sgblack@eecs.umich.edu dest2(_dest2) 3237279Sgblack@eecs.umich.edu {} 3247279Sgblack@eecs.umich.edu 3257279Sgblack@eecs.umich.edu void 3267279Sgblack@eecs.umich.edu printDest(std::ostream &os) const 3277279Sgblack@eecs.umich.edu { 3287279Sgblack@eecs.umich.edu MemoryReg::printDest(os); 3297279Sgblack@eecs.umich.edu os << ", "; 33012104Snathanael.premillieu@arm.com printIntReg(os, dest2); 3317279Sgblack@eecs.umich.edu } 3327279Sgblack@eecs.umich.edu}; 3337279Sgblack@eecs.umich.edu 3347118Sgblack@eecs.umich.edutemplate<class Base> 3357132Sgblack@eecs.umich.educlass MemoryOffset : public Base 3367118Sgblack@eecs.umich.edu{ 3377118Sgblack@eecs.umich.edu protected: 3387132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3397132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3407132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 3417132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3427132Sgblack@eecs.umich.edu {} 3437132Sgblack@eecs.umich.edu 3447132Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3457132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3467132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3477132Sgblack@eecs.umich.edu IntRegIndex _index) 3487132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3497132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3507132Sgblack@eecs.umich.edu {} 3517132Sgblack@eecs.umich.edu 3527279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3537279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3547279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3557279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3567279Sgblack@eecs.umich.edu {} 3577279Sgblack@eecs.umich.edu 3587279Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3597303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 3607303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 3617303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3627303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 3637303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 3647303Sgblack@eecs.umich.edu {} 3657303Sgblack@eecs.umich.edu 3667303Sgblack@eecs.umich.edu MemoryOffset(const char *mnem, ExtMachInst _machInst, 3677279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3687279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 3697279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3707279Sgblack@eecs.umich.edu IntRegIndex _index) 3717279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3727279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 3737279Sgblack@eecs.umich.edu {} 3747279Sgblack@eecs.umich.edu 3757132Sgblack@eecs.umich.edu std::string 3767132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3777132Sgblack@eecs.umich.edu { 3787132Sgblack@eecs.umich.edu std::stringstream ss; 3797132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_Offset); 3807132Sgblack@eecs.umich.edu return ss.str(); 3817132Sgblack@eecs.umich.edu } 3827132Sgblack@eecs.umich.edu}; 3837132Sgblack@eecs.umich.edu 3847132Sgblack@eecs.umich.edutemplate<class Base> 3857132Sgblack@eecs.umich.educlass MemoryPreIndex : public Base 3867132Sgblack@eecs.umich.edu{ 3877132Sgblack@eecs.umich.edu protected: 3887132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3897132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3907132Sgblack@eecs.umich.edu bool _add, int32_t _imm) 3917132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3927132Sgblack@eecs.umich.edu {} 3937132Sgblack@eecs.umich.edu 3947132Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3957132Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3967132Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3977132Sgblack@eecs.umich.edu IntRegIndex _index) 3987132Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3997132Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4007132Sgblack@eecs.umich.edu {} 4017132Sgblack@eecs.umich.edu 4027279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4037279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4047279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4057279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 4067279Sgblack@eecs.umich.edu {} 4077279Sgblack@eecs.umich.edu 4087279Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4097303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 4107303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 4117303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4127303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 4137303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 4147303Sgblack@eecs.umich.edu {} 4157303Sgblack@eecs.umich.edu 4167303Sgblack@eecs.umich.edu MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 4177279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4187279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 4197279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 4207279Sgblack@eecs.umich.edu IntRegIndex _index) 4217279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4227279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4237279Sgblack@eecs.umich.edu {} 4247279Sgblack@eecs.umich.edu 4257132Sgblack@eecs.umich.edu std::string 4267132Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4277132Sgblack@eecs.umich.edu { 4287132Sgblack@eecs.umich.edu std::stringstream ss; 4297132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PreIndex); 4307132Sgblack@eecs.umich.edu return ss.str(); 4317132Sgblack@eecs.umich.edu } 4327132Sgblack@eecs.umich.edu}; 4337132Sgblack@eecs.umich.edu 4347132Sgblack@eecs.umich.edutemplate<class Base> 4357132Sgblack@eecs.umich.educlass MemoryPostIndex : public Base 4367132Sgblack@eecs.umich.edu{ 4377132Sgblack@eecs.umich.edu protected: 4387132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4397118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4407118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 4417118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 4427118Sgblack@eecs.umich.edu {} 4437118Sgblack@eecs.umich.edu 4447132Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4457118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 4467118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 4477118Sgblack@eecs.umich.edu IntRegIndex _index) 4487118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 4497118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4507118Sgblack@eecs.umich.edu {} 4517118Sgblack@eecs.umich.edu 4527279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4537279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4547279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4557279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 4567279Sgblack@eecs.umich.edu {} 4577279Sgblack@eecs.umich.edu 4587279Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4597303Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _result, 4607303Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _dest2, 4617303Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, int32_t _imm) 4627303Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _result, 4637303Sgblack@eecs.umich.edu _dest, _dest2, _base, _add, _imm) 4647303Sgblack@eecs.umich.edu {} 4657303Sgblack@eecs.umich.edu 4667303Sgblack@eecs.umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 4677279Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 4687279Sgblack@eecs.umich.edu IntRegIndex _base, bool _add, 4697279Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 4707279Sgblack@eecs.umich.edu IntRegIndex _index) 4717279Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 4727279Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 4737279Sgblack@eecs.umich.edu {} 4747279Sgblack@eecs.umich.edu 4757118Sgblack@eecs.umich.edu std::string 4767118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 4777118Sgblack@eecs.umich.edu { 4787118Sgblack@eecs.umich.edu std::stringstream ss; 4797132Sgblack@eecs.umich.edu this->printInst(ss, Memory::AddrMd_PostIndex); 4807118Sgblack@eecs.umich.edu return ss.str(); 4817118Sgblack@eecs.umich.edu } 4827118Sgblack@eecs.umich.edu}; 4836253Sgblack@eecs.umich.edu} 4846253Sgblack@eecs.umich.edu 4856253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MEM_HH__ 486