/gem5/src/arch/arm/ |
H A D | tlbi_op.hh | 127 : TLBIOp(_targetEL, _secure), asid(_asid) 133 uint16_t asid; member in class:ArmISA::TLBIASID 141 : TLBIOp(_targetEL, _secure), asid(_asid) 149 uint16_t asid; member in class:ArmISA::ITLBIASID 157 : TLBIOp(_targetEL, _secure), asid(_asid) 165 uint16_t asid; member in class:ArmISA::DTLBIASID 200 : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid) 207 uint16_t asid; member in class:ArmISA::TLBIMVA 216 : TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid) 225 uint16_t asid; member in class:ArmISA::ITLBIMVA 243 uint16_t asid; member in class:ArmISA::DTLBIMVA [all...] |
H A D | tlbi_op.cc | 78 getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 79 getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 82 getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 83 getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 90 getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 96 getDTBPtr(tc)->flushAsid(asid, secureLookup, targetEL); 128 getITBPtr(tc)->flushMvaAsid(addr, asid, 130 getDTBPtr(tc)->flushMvaAsid(addr, asid, 136 addr, asid, secureLookup, targetEL); 138 addr, asid, secureLooku [all...] |
H A D | pagetable.hh | 113 uint16_t asid; // Address Space Identifier member in struct:ArmISA::TlbEntry 153 attributes(0), lookupLevel(L1), asid(_asn), vmid(0), N(0), 168 pfn(0), size(0), vpn(0), attributes(0), lookupLevel(L1), asid(0), 212 match = global || (asn == asid); 290 "ns:%d nstid:%d g:%d el:%d", vpn << N, asid, vmid, 301 SERIALIZE_SCALAR(asid); variable 331 UNSERIALIZE_SCALAR(asid); variable
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H A D | tlb.cc | 82 isHyp(false), asid(0), vmid(0), hcr(0), dacr(0), 127 TlbEntry *e = lookup(va, asid, vmid, isHyp, isSecure, true, false, 181 "ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d " 187 retval ? retval->global : 0, retval ? retval->asid : 0, 198 " asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d" 200 entry.size, entry.vpn, entry.asid, entry.vmid, entry.N, 208 table[size-1].vpn << table[size-1].N, table[size-1].asid, 305 DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x " 315 DPRINTF(TLB, "Flushing TLB entries with asid: %#x (%s lookup)\n", asn, 323 if (te->valid && te->asid [all...] |
/gem5/src/arch/riscv/ |
H A D | pagetable.cc | 46 SERIALIZE_SCALAR(asid); 65 UNSERIALIZE_SCALAR(asid);
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H A D | pagetable.hh | 52 uint8_t asid; member in struct:RiscvISA::PTE
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H A D | tlb.cc | 96 (pte->G || (asn == pte->asid))) { 134 (pte->G || (asn == pte->asid))) { 142 DPRINTF(RiscvTLB,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 170 ((pte.VPN << 11) | pte.asid),
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H A D | pra_constants.hh | 101 Bitfield<7, 0> asid; member in namespace:RiscvISA 287 Bitfield<23, 16> asid; member in namespace:RiscvISA
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/gem5/src/arch/mips/ |
H A D | pagetable.cc | 46 SERIALIZE_SCALAR(asid); 65 UNSERIALIZE_SCALAR(asid);
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H A D | faults.hh | 228 Addr asid; member in class:MipsISA::TlbFault 232 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn) 242 entryHi.asid = this->asid; 276 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument 277 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store) 291 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument 292 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store) 299 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) : argument 300 TlbFault<TlbModifiedFault>(asid, vadd [all...] |
H A D | pagetable.hh | 52 uint8_t asid; member in struct:MipsISA::PTE
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H A D | mt_constants.hh | 95 Bitfield<7, 0> asid; member in namespace:MipsISA
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H A D | tlb.cc | 94 (pte->G || (asn == pte->asid))) { 132 (pte->G || (asn == pte->asid))) { 140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind); 168 ((pte.VPN << 11) | pte.asid),
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H A D | dt_constants.hh | 84 Bitfield<12, 5> asid; member in namespace:MipsISA
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H A D | pra_constants.hh | 101 Bitfield<7, 0> asid; member in namespace:MipsISA 287 Bitfield<23, 16> asid; member in namespace:MipsISA
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/gem5/src/arch/power/ |
H A D | pagetable.cc | 50 SERIALIZE_SCALAR(asid); 69 UNSERIALIZE_SCALAR(asid);
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H A D | pagetable.hh | 120 uint8_t asid; member in struct:PowerISA::PTE
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H A D | tlb.cc | 96 && (pte->G || (asn == pte->asid))) { 133 && (pte->G || (asn == pte->asid))) { 143 DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
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/gem5/src/dev/arm/ |
H A D | smmu_v3_caches.hh | 114 uint16_t asid; member in struct:SMMUTLB::Entry 135 void invalidateVA(Addr va, uint16_t asid, uint16_t vmid); 137 void invalidateASID(uint16_t asid, uint16_t vmid); 163 uint16_t asid; member in struct:ARMArchTLB::Entry 175 const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid, 180 void invalidateVA(Addr va, uint16_t asid, uint16_t vmid); 182 void invalidateASID(uint16_t asid, uint16_t vmid); 192 size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const; 254 uint16_t asid; member in struct:ConfigCache::Entry 294 uint16_t asid; member in struct:WalkCache::Entry [all...] |
H A D | smmu_v3_caches.cc | 289 SMMUTLB::invalidateVA(Addr va, uint16_t asid, uint16_t vmid) argument 297 e.asid==asid && e.vmid==vmid) 318 SMMUTLB::invalidateASID(uint16_t asid, uint16_t vmid) argument 326 if (e.asid==asid && e.vmid==vmid) 459 ARMArchTLB::lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats) argument 463 Set &set = sets[pickSetIdx(va, asid, vmid)]; 469 e.asid==asid 513 invalidateVA(Addr va, uint16_t asid, uint16_t vmid) argument 544 invalidateASID(uint16_t asid, uint16_t vmid) argument 585 pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const argument 1014 lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats) argument 1086 invalidateVA(Addr va, uint16_t asid, uint16_t vmid, const bool leaf_only) argument 1123 invalidateASID(uint16_t asid, uint16_t vmid) argument [all...] |
H A D | smmu_v3_transl.cc | 384 smmu.tlb.lookup(request.addr, context.asid, context.vmid); 388 DPRINTF(SMMUv3, "SMMU TLB miss vaddr=%#x asid=%#x vmid=%#x\n", 389 request.addr, context.asid, context.vmid); 395 "SMMU TLB hit vaddr=%#x amask=%#x asid=%#x vmid=%#x paddr=%#x\n", 396 request.addr, e->vaMask, context.asid, context.vmid, e->pa); 424 e.asid = context.asid; 456 e.asid = context.asid; 488 e.asid 647 walkCacheLookup( Yield &yield, const WalkCache::Entry *&walkEntry, Addr addr, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level) argument [all...] |
H A D | smmu_v3_transl.hh | 72 uint16_t asid; member in struct:SMMUTranslationProcess::TranslContext 122 Addr addr, uint16_t asid, uint16_t vmid,
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H A D | smmu_v3.cc | 471 DPRINTF(SMMUv3, "CMD_TLBI_NH_ASID asid=%#x vmid=%#x\n", 472 cmd.dw0.asid, cmd.dw0.vmid); 475 cmd.dw0.asid, cmd.dw0.vmid); 477 cmd.dw0.asid, cmd.dw0.vmid); 479 tlb.invalidateASID(cmd.dw0.asid, cmd.dw0.vmid); 480 walkCache.invalidateASID(cmd.dw0.asid, cmd.dw0.vmid); 502 DPRINTF(SMMUv3, "CMD_TLBI_NH_VA va=%#08x asid=%#x vmid=%#x\n", 503 addr, cmd.dw0.asid, cmd.dw0.vmid); 506 addr, cmd.dw0.asid, cmd.dw0.vmid); 508 addr, cmd.dw0.asid, cm [all...] |
/gem5/src/mem/ |
H A D | request.hh | 268 /** Whether or not the vaddr & asid are valid. */ 459 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument 467 setVirt(asid, vaddr, size, flags, mid, pc); 471 Request(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument 475 setVirt(asid, vaddr, size, flags, mid, pc, std::move(atomic_op)); 529 setVirt(uint64_t asid, Addr vaddr, unsigned size, Flags flags, argument 532 _asid = asid; 734 /** Accessor function for asid.*/ 742 /** Accessor function for asid.*/ 744 setAsid(uint64_t asid) argument [all...] |
/gem5/src/cpu/o3/probe/ |
H A D | elastic_trace.hh | 297 uint32_t asid; member in struct:ElasticTrace::TraceInfo
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