1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Jaidev Patwardhan
34 *          Stephen Hines
35 *          Timothy M. Jones
36 */
37
38#ifndef __ARCH_POWER_PAGETABLE_H__
39#define __ARCH_POWER_PAGETABLE_H__
40
41#include "arch/power/isa_traits.hh"
42#include "arch/power/utility.hh"
43#include "arch/power/vtophys.hh"
44
45namespace PowerISA {
46
47struct VAddr
48{
49    static const int ImplBits = 43;
50    static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
51    static const Addr UnImplMask = ~ImplMask;
52
53    Addr addr;
54
55    VAddr(Addr a)
56        : addr(a)
57    {}
58
59    operator Addr() const
60    {
61        return addr;
62    }
63
64    const VAddr
65    &operator=(Addr a)
66    {
67        addr = a;
68        return *this;
69    }
70
71    Addr
72    vpn() const
73    {
74        return (addr & ImplMask) >> PageShift;
75    }
76
77    Addr
78    page() const
79    {
80        return addr & Page_Mask;
81    }
82
83    Addr
84    offset() const
85    {
86        return addr & PageOffset;
87    }
88
89    Addr
90    level3() const
91    {
92        return PowerISA::PteAddr(addr >> PageShift);
93    }
94
95    Addr
96    level2() const
97    {
98        return PowerISA::PteAddr(addr >> (NPtePageShift + PageShift));
99    }
100
101    Addr
102    level1() const
103    {
104        return PowerISA::PteAddr(addr >> (2 * NPtePageShift + PageShift));
105    }
106};
107
108// ITB/DTB page table entry
109struct PTE
110{
111    // What parts of the VAddr (from bits 28..11) should be used in
112    // translation (includes Mask and MaskX from PageMask)
113    Addr Mask;
114
115    // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11
116    // from EntryHi)
117    Addr VPN;
118
119    // Address Space ID (8 bits) // Lower 8 bits of EntryHi
120    uint8_t asid;
121
122    // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
123    bool G;
124
125    /* Contents of Entry Lo0 */
126    Addr PFN0; // Physical Frame Number - Even
127    bool D0;   // Even entry Dirty Bit
128    bool V0;   // Even entry Valid Bit
129    uint8_t C0; // Cache Coherency Bits - Even
130
131    /* Contents of Entry Lo1 */
132    Addr PFN1; // Physical Frame Number - Odd
133    bool D1;   // Odd entry Dirty Bit
134    bool V1;   // Odd entry Valid Bit
135    uint8_t C1; // Cache Coherency Bits (3 bits)
136
137    // The next few variables are put in as optimizations to reduce TLB
138    // lookup overheads. For a given Mask, what is the address shift amount
139    // and what is the OffsetMask
140    int AddrShiftAmount;
141    int OffsetMask;
142
143    bool
144    Valid()
145    {
146        return (V0 | V1);
147    };
148
149    void serialize(CheckpointOut &cp) const;
150    void unserialize(CheckpointIn &cp);
151};
152
153} // namespace PowerISA
154
155#endif // __ARCH_POWER_PAGETABLE_H__
156
157