Searched refs:xc (Results 1 - 25 of 40) sorted by relevance

12

/gem5/src/arch/sparc/
H A Dmmapped_ipr.hh49 handleIprRead(ThreadContext *xc, Packet *pkt) argument
52 return GenericISA::handleGenericIprRead(xc, pkt);
54 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
58 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
61 return GenericISA::handleGenericIprWrite(xc, pkt);
63 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
/gem5/src/arch/arm/
H A Dlocked_mem.hh65 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
71 xc->getCpuPtr()->name(),pkt->getAddr(),
72 xc->readMiscReg(MISCREG_LOCKFLAG));
73 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
81 xc->getCpuPtr()->name(),snoop_addr, locked_addr);
84 xc->getCpuPtr()->name());
85 xc->setMiscReg(MISCREG_LOCKFLAG, false);
87 xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
88 xc
94 handleLockedRead(XC *xc, const RequestPtr &req) argument
104 handleLockedSnoopHit(XC *xc) argument
114 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
153 globalClearExclusive(XC *xc) argument
[all...]
/gem5/src/arch/alpha/
H A Dlocked_mem.hh69 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
75 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
82 xc->setMiscReg(MISCREG_LOCKFLAG, false);
88 handleLockedRead(XC *xc, const RequestPtr &req) argument
90 xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
91 xc->setMiscReg(MISCREG_LOCKFLAG, true);
96 handleLockedSnoopHit(XC *xc) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
110 bool lock_flag = xc
140 globalClearExclusive(XC *xc) argument
[all...]
/gem5/src/arch/mips/
H A Dlocked_mem.hh63 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
65 if (!xc->readMiscReg(MISCREG_LLFLAG))
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
72 xc->setMiscReg(MISCREG_LLFLAG, false);
78 handleLockedRead(XC *xc, const RequestPtr &req) argument
80 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
81 xc->setMiscReg(MISCREG_LLFLAG, true);
89 handleLockedSnoopHit(XC *xc) argument
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
103 bool lock_flag = xc
144 globalClearExclusive(XC *xc) argument
[all...]
/gem5/src/arch/generic/
H A Dlocked_mem.hh60 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
66 handleLockedRead(XC *xc, const RequestPtr &req) argument
72 handleLockedSnoopHit(XC *xc) argument
79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
86 globalClearExclusive(XC *xc) argument
H A Dmmapped_ipr.hh113 * @param xc Thread context of the current thread.
117 Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt);
121 * @param xc Thread context of the current thread.
125 Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt);
134 * @param xc Thread context of the current thread.
139 handleIprRead(ThreadContext *xc, Packet *pkt) argument
144 return handleGenericIprRead(xc, pkt);
155 * @param xc Thread context of the current thread.
160 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
165 return handleGenericIprWrite(xc, pk
[all...]
H A Dmmapped_ipr.cc42 handlePseudoInst(ThreadContext *xc, Packet *pkt) argument
50 ret = PseudoInst::pseudoInst(xc, func, subfunc);
56 GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt) argument
63 handlePseudoInst(xc, pkt);
73 GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt) argument
80 handlePseudoInst(xc, pkt);
H A Dmemhelpers.hh58 initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, argument
61 return xc->initiateMemRead(addr, sizeof(MemT), flags);
77 readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, argument
81 Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
93 writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, argument
100 return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
106 writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, argument
114 xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
127 amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, argument
136 Fault fault = xc
150 initiateMemAMO(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT& mem, Request::Flags flags, AtomicOpFunctor *_amo_op) argument
[all...]
/gem5/src/arch/riscv/
H A Dlocked_mem.hh74 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
76 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
88 handleLockedRead(XC *xc, const RequestPtr &req) argument
90 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
98 handleLockedSnoopHit(XC *xc) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
104 std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
122 int stCondFailures = xc->readStCondFailures();
123 xc->setStCondFailures(++stCondFailures);
126 curTick(), xc
138 globalClearExclusive(XC *xc) argument
[all...]
/gem5/src/arch/x86/
H A Dmmapped_ipr.hh58 handleIprRead(ThreadContext *xc, Packet *pkt) argument
61 return GenericISA::handleGenericIprRead(xc, pkt);
66 RegVal data = htog(xc->readMiscReg(index));
75 handleIprWrite(ThreadContext *xc, Packet *pkt) argument
78 return GenericISA::handleGenericIprWrite(xc, pkt);
83 RegVal data = htog(xc->readMiscRegNoEffect(index));
87 xc->setMiscReg(index, gtoh(data));
H A Dmemhelpers.hh47 initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, argument
50 return xc->initiateMemRead(addr, dataSize, flags);
107 readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, argument
111 Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
125 readPackedMemAtomic(ExecContext *xc, Addr addr, std::array<uint64_t, N> &mem, argument
129 Fault fault = xc->readMem(addr, (uint8_t *)&real_mem,
141 readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr, argument
149 fault = readPackedMemAtomic<uint32_t, N>(xc, addr, mem, flags);
152 fault = readPackedMemAtomic<uint64_t, N>(xc, addr, mem, flags);
164 writePackedMem(ExecContext *xc, st argument
176 writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) argument
188 writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, std::array<uint64_t, N> &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) argument
206 writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res) argument
222 writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, std::array<uint64_t, N> &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res) argument
[all...]
/gem5/src/kern/freebsd/
H A Devents.hh63 virtual void process(ThreadContext *xc);
/gem5/src/kern/linux/
H A Devents.hh56 virtual void process(ThreadContext *xc);
76 virtual void process(ThreadContext *xc);
96 virtual void process(ThreadContext *xc);
122 virtual void process(ThreadContext *xc);
/gem5/src/arch/arm/insts/
H A Dpseudo.hh59 Fault execute(ExecContext *xc,
85 Fault execute(ExecContext *xc,
115 Fault execute(ExecContext *xc,
134 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
H A Dpseudo.cc59 DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const argument
61 const PCState pc_state(xc->pcState());
131 FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const argument
166 WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const argument
189 IllegalExecInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const argument
H A Dstatic_inst.hh299 readPC(ExecContext *xc) argument
301 return xc->pcState().instPC();
305 setNextPC(ExecContext *xc, Addr val) argument
307 PCState pc = xc->pcState();
309 xc->pcState(pc);
347 setIWNextPC(ExecContext *xc, Addr val) argument
349 PCState pc = xc->pcState();
351 xc->pcState(pc);
357 setAIWNextPC(ExecContext *xc, Addr val) argument
359 PCState pc = xc
[all...]
/gem5/src/arch/sparc/insts/
H A Dunimp.hh64 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
100 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
H A Dnop.hh59 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
H A Dnop.cc54 execute(ExecContext *xc, Trace::InstRecord *traceData) const argument
75 Fault %(class_name)s::execute(ExecContext *xc, argument
/gem5/src/arch/riscv/insts/
H A Dstatic_inst.hh88 initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
94 completeAcc(PacketPtr pkt, ExecContext *xc,
101 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
H A Damo.cc55 Fault MemFenceMicro::execute(ExecContext *xc, argument
/gem5/src/cpu/
H A Dtranslation.hh221 ExecContextPtr xc; member in class:DataTranslation
227 : xc(_xc), state(_state), index(0)
233 : xc(_xc), state(_state), index(_index)
262 xc->finishTranslation(state);
270 return xc->isSquashed();
H A Dstatic_inst.cc49 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
/gem5/src/sim/
H A Dpseudo_inst.hh76 void loadsymbol(ThreadContext *xc);
78 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
/gem5/src/dev/x86/
H A Di8237.cc113 case 0xc:

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