/gem5/src/arch/arm/ |
H A D | vtophys.cc | 52 #include "arch/arm/tlb.hh" 74 ArmISA::TLB *tlb; local 77 // It's possible that there is a valid translation in the tlb 83 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr()); 84 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran); 88 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr()); 89 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
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H A D | ArmTLB.py | 66 cxx_header = "arch/arm/tlb.hh" 85 tlb = Param.ArmTLB("Stage 1 TLB") variable in class:ArmStage2MMU 93 tlb = Parent.itb variable in class:ArmStage2IMMU 99 tlb = Parent.dtb variable in class:ArmStage2DMMU
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H A D | tlb.hh | 51 #include "arch/generic/tlb.hh" 470 auto tlb = static_cast<TLB *>(tc->getITBPtr()); local 471 assert(tlb); 472 return tlb; 479 auto tlb = static_cast<TLB *>(tc->getDTBPtr()); local 480 assert(tlb); 481 return tlb;
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H A D | stage2_mmu.cc | 45 #include "arch/arm/tlb.hh" 52 : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
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H A D | table_walker.hh | 49 #include "arch/arm/tlb.hh" 839 TLB *tlb; member in class:ArmISA::TableWalker::LongDescriptor 912 void setTlb(TLB *_tlb) { tlb = _tlb; } 913 TLB* getTlb() { return tlb; }
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H A D | table_walker.cc | 47 #include "arch/arm/tlb.hh" 62 isStage2(p->is_stage2), tlb(NULL), 114 fatal_if(!tlb, "Table walker must have a valid TLB\n"); 372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, 427 tlb->translateTiming(currState->req, currState->tc, 438 te = tlb->lookup(currState->vaddr, currState->asid, 1827 tlb->translateTiming(currState->req, currState->tc, 1868 tlb->translateTiming(currState->req, currState->tc, 1945 tlb->translateTiming(currState->req, currState->tc, 2116 tlb [all...] |
/gem5/src/arch/sparc/ |
H A D | tlb.cc | 31 #include "arch/sparc/tlb.hh" 63 tlb = new TlbEntry[size]; 64 std::memset((void *)tlb, 0, sizeof(TlbEntry) * size); 67 freeList.push_back(&tlb[x]); 120 if (tlb[x].range.real == real && 121 tlb[x].range.partitionId == partition_id && 122 tlb[x].range.va < va + PTE.size() - 1 && 123 tlb[x].range.va + tlb[x].range.size >= va && 124 (real || tlb[ [all...] |
H A D | tlb.hh | 34 #include "arch/generic/tlb.hh" 54 // These faults need to be able to populate the tlb in SE mode. 75 TlbEntry *tlb; member in class:SparcISA::TLB 117 * @return A pointer to a tlb entry 130 /** Given an entry id, read that tlb entries' tag. */ 133 /** Remove all non-locked entries from the tlb that match partition id. */ 187 /** Give an entry id, read that tlb entries' tte */
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/gem5/src/arch/x86/ |
H A D | tlb.cc | 40 #include "arch/x86/tlb.hh" 64 tlb(size), lruSeq(0) 70 tlb[x].trieHandle = NULL; 71 freeList.push_back(&tlb[x]); 86 if (tlb[i].lruSeq < tlb[lru].lruSeq) 90 assert(tlb[lru].trieHandle); 91 trie.remove(tlb[lru].trieHandle); 92 tlb[lru].trieHandle = NULL; 93 freeList.push_back(&tlb[lr [all...] |
H A D | pagetable_walker.hh | 46 #include "arch/x86/tlb.hh" 171 TLB * tlb; member in class:X86ISA::Walker 195 tlb = _tlb; 208 funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
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H A D | tlb.hh | 46 #include "arch/generic/tlb.hh" 96 std::vector<TlbEntry> tlb; member in class:X86ISA::TLB
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H A D | pagetable_walker.cc | 57 #include "arch/x86/tlb.hh" 516 walker->tlb->insert(entry.vaddr, entry); 644 Fault fault = walker->tlb->translate(req, tc, NULL, mode,
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.hh | 45 #include "arch/generic/tlb.hh" 162 std::vector<TlbEntry> tlb; member in class:X86ISA::GpuTLB 264 : SlavePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { } 267 GpuTLB *tlb; member in class:X86ISA::GpuTLB::CpuSidePort 291 : MasterPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { } 296 GpuTLB *tlb; member in class:X86ISA::GpuTLB::MemSidePort 385 GpuTLB *tlb; member in class:X86ISA::GpuTLB::TLBEvent
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H A D | gpu_tlb.cc | 77 tlb.assign(size, TlbEntry()); 85 freeList[set].push_back(&tlb.at(x)); 681 // functional tlb access for memory initialization 1115 : Event(CPU_Tick_Pri), tlb(_tlb), virtPageAddr(_addr), 1359 tlb->translationReturn(virtPageAddr, outcome, pkt); 1389 if (tlb->outstandingReqs < tlb->maxCoalescedReqs) { 1390 tlb->issueTLBLookup(pkt); 1392 tlb->outstandingReqs++; 1396 tlb [all...] |
H A D | dispatcher.hh | 96 TranslationBuffer tlb; member in class:GpuDispatcher
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/gem5/configs/common/ |
H A D | GPUTLBConfig.py | 166 for tlb in range(tlb_per_cu): 169 (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0))
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/gem5/src/arch/alpha/ |
H A D | ev5.cc | 36 #include "arch/alpha/tlb.hh" 50 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr()); local 51 assert(tlb); 52 return tlb; 59 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr()); local 60 assert(tlb); 61 return tlb;
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/gem5/src/mem/cache/prefetch/ |
H A D | base.hh | 55 #include "arch/generic/tlb.hh" 330 /** Registered tlb for address translations */ 331 BaseTLB * tlb; member in class:BasePrefetcher 383 * @param tlb pointer to the BaseTLB object to add 385 void addTLB(BaseTLB *tlb);
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H A D | queued.cc | 44 #include "arch/generic/tlb.hh" 73 QueuedPrefetcher::DeferredPacket::startTranslation(BaseTLB *tlb) argument 79 tlb->translateTiming(translationRequest, tc, this, BaseTLB::Read); 180 bool can_cross_page = (tlb != nullptr); 263 dp.startTranslation(tlb); 281 "paddr %#x \n", tlb->name(), 299 "prefetch request %#x \n", tlb->name(),
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H A D | base.cc | 99 usefulPrefetches(0), tlb(nullptr) 261 fatal_if(tlb != nullptr, "Only one TLB can be registered"); 262 tlb = t;
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H A D | queued.hh | 129 * @param tlb the tlb that has to translate the address 131 void startTranslation(BaseTLB *tlb);
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H A D | Prefetcher.py | 92 for tlb in self._tlbs: 93 self.getCCObject().addTLB(tlb.getCCObject())
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/gem5/src/dev/arm/ |
H A D | smmu_v3.hh | 99 ARMArchTLB tlb; member in class:SMMUv3
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H A D | smmu_v3.cc | 63 tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy), 465 tlb.invalidateVMID(cmd.dw0.vmid); 479 tlb.invalidateASID(cmd.dw0.asid, cmd.dw0.vmid); 494 tlb.invalidateVAA(addr, cmd.dw0.vmid); 510 tlb.invalidateVA(addr, cmd.dw0.asid, cmd.dw0.vmid); 536 tlb.invalidateVMID(cmd.dw0.vmid); 548 tlb.invalidateAll(); 753 tlb.regStats(name() + ".tlb");
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H A D | smmu_v3_caches.hh | 124 SMMUTLB(const SMMUTLB& tlb) = delete; member in class:SMMUTLB
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