Lines Matching refs:tlb
47 #include "arch/arm/tlb.hh"
62 isStage2(p->is_stage2), tlb(NULL),
114 fatal_if(!tlb, "Table walker must have a valid TLB\n");
372 TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid,
427 tlb->translateTiming(currState->req, currState->tc,
438 te = tlb->lookup(currState->vaddr, currState->asid,
1827 tlb->translateTiming(currState->req, currState->tc,
1868 tlb->translateTiming(currState->req, currState->tc,
1945 tlb->translateTiming(currState->req, currState->tc,
2116 tlb->insert(currState->vaddr, te);
2166 return tlb->testWalk(pa, size, currState->vaddr, currState->isSecure,