| /gem5/src/cpu/o3/ |
| H A D | FuncUnitConfig.py | 48 opList = [ OpDesc(opClass='IntAlu') ]
52 opList = [ OpDesc(opClass='IntMult', opLat=3),
53 OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
66 OpDesc(opClass='FloatCmp', opLat=2),
67 OpDesc(opClass='FloatCvt', opLat=2) ]
71 opList = [ OpDesc(opClass='FloatMult', opLat=4),
72 OpDesc(opClass='FloatMultAcc', opLat=5),
73 OpDesc(opClass='FloatMisc', opLat=3),
74 OpDesc(opClass
[all...] |
| H A D | fu_pool.cc | 117 capabilityList.set((*j)->opClass);
122 fuPerCapList[(*j)->opClass].addFU(numFU + k);
125 fu->addCapability((*j)->opClass, (*j)->opLat, (*j)->pipelined);
127 if ((*j)->opLat > maxOpLatencies[(*j)->opClass])
128 maxOpLatencies[(*j)->opClass] = (*j)->opLat;
131 pipelined[(*j)->opClass] = false;
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| H A D | inst_queue_impl.hh | 1087 OpClass op_class = ready_inst->opClass();
1470 OpClass op_class = inst->opClass();
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| H A D | commit_impl.hh | 1048 statCommittedInstType[tid][head_inst->opClass()]++;
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| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=4) ]
47 opList = [ OpDesc(opClass='IntMult', opLat=7) ]
50 opList = [ OpDesc(opClass='IntDiv', opLat=9) ]
54 opList = [ OpDesc(opClass='SimdAdd', opLat=6),
55 OpDesc(opClass='SimdAddAcc', opLat=4),
56 OpDesc(opClass='SimdAlu', opLat=4),
57 OpDesc(opClass='SimdCmp', opLat=1),
58 OpDesc(opClass='SimdCvt', opLat=3),
59 OpDesc(opClass='SimdMisc', opLat=3),
60 OpDesc(opClass
[all...] |
| H A D | O3_ARM_v7a.py | 36 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
41 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
42 OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
43 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
49 opList = [ OpDesc(opClass='SimdAdd', opLat=4),
50 OpDesc(opClass='SimdAddAcc', opLat=4),
51 OpDesc(opClass='SimdAlu', opLat=4),
52 OpDesc(opClass='SimdCmp', opLat=4),
53 OpDesc(opClass='SimdCvt', opLat=3),
54 OpDesc(opClass
[all...] |
| H A D | ex5_big.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
48 opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
49 OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
50 OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
55 opList = [ OpDesc(opClass='SimdAdd', opLat=3),
56 OpDesc(opClass='SimdAddAcc', opLat=4),
57 OpDesc(opClass='SimdAlu', opLat=4),
58 OpDesc(opClass='SimdCmp', opLat=4),
59 OpDesc(opClass='SimdCvt', opLat=3),
60 OpDesc(opClass
[all...] |
| /gem5/src/cpu/ |
| H A D | FuncUnit.py | 65 opClass = Param.OpClass("type of operation") variable in class:OpDesc
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| H A D | func_unit.hh | 54 OpClass opClass; member in class:OpDesc
59 : SimObject(p), opClass(p->opClass), opLat(p->opLat),
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| H A D | inst_pb_trace.cc | 162 curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
171 curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
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| H A D | exetrace.cc | 125 outs << Enums::OpClassStrings[inst->opClass()] << " : ";
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| H A D | static_inst.hh | 99 /// See opClass().
211 OpClass opClass() const { return _opClass; } function in class:StaticInst
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| H A D | base_dyn_inst.hh | 577 OpClass opClass() const { return staticInst->opClass(); } function in class:BaseDynInst
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| /gem5/src/cpu/minor/ |
| H A D | func_unit.hh | 64 OpClass opClass; member in class:MinorOpClass
69 opClass(params->opClass)
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| H A D | func_unit.cc | 87 capabilityList[opClasses[i]->opClass] = true;
131 addCapability(description.opClasses->opClasses[i]->opClass,
220 if (timing.provides(inst->opClass()) &&
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| H A D | dyn_inst.cc | 101 return isInst() && staticInst->opClass() == No_OpClass;
231 (staticInst->opClass() == No_OpClass ?
233 Enums::OpClassStrings[staticInst->opClass()],
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| H A D | MinorCPU.py | 63 opClass = Param.OpClass("op class to match") variable in class:MinorOpClass
103 return MinorOpClass(opClass=op_class)
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| H A D | execute.cc | 615 fu->provides(inst->staticInst->opClass()) : true);
880 [inst->staticInst->opClass()]++;
1532 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) &&
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| /gem5/src/cpu/simple/ |
| H A D | base.cc | 654 t_info.statExecutedInstType[curStaticInst->opClass()]++;
|