12SN/A/* 21762SN/A * Copyright (c) 2013-2014 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 331110SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352680Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362196SN/A * 372196SN/A * Authors: Andrew Bardsley 384997Sgblack@eecs.umich.edu */ 392800Ssaidi@eecs.umich.edu 402800Ssaidi@eecs.umich.edu/** 412289SN/A * @file 422SN/A * 435569Snate@binkert.org * Execute function unit descriptions and pipeline implementations. 442167SN/A */ 452203SN/A 462203SN/A#ifndef __CPU_MINOR_FUNC_UNIT_HH__ 472222SN/A#define __CPU_MINOR_FUNC_UNIT_HH__ 482166SN/A 492203SN/A#include "cpu/minor/buffers.hh" 502203SN/A#include "cpu/minor/dyn_inst.hh" 512222SN/A#include "cpu/func_unit.hh" 522166SN/A#include "cpu/timing_expr.hh" 532147SN/A#include "params/MinorFU.hh" 542147SN/A#include "params/MinorFUPool.hh" 552222SN/A#include "params/MinorOpClass.hh" 562147SN/A#include "params/MinorOpClassSet.hh" 572147SN/A#include "sim/clocked_object.hh" 582147SN/A 592222SN/A/** Boxing for MinorOpClass to get around a build problem with C++11 but 602147SN/A * also allow for future additions to op class checking */ 612147SN/Aclass MinorOpClass : public SimObject 622147SN/A{ 632222SN/A public: 642147SN/A OpClass opClass; 652147SN/A 662147SN/A public: 672222SN/A MinorOpClass(const MinorOpClassParams *params) : 682147SN/A SimObject(params), 692147SN/A opClass(params->opClass) 702147SN/A { } 712222SN/A}; 722147SN/A 732147SN/A/** Wrapper for a matchable set of op classes */ 742147SN/Aclass MinorOpClassSet : public SimObject 752222SN/A{ 762147SN/A public: 772147SN/A std::vector<MinorOpClass *> opClasses; 782147SN/A 792222SN/A /** Convenience packing of opClasses into a bit vector for easier 802147SN/A * testing */ 812289SN/A std::vector<bool> capabilityList; 822289SN/A 832289SN/A public: 842289SN/A MinorOpClassSet(const MinorOpClassSetParams *params); 852147SN/A 862147SN/A public: 872222SN/A /** Does this set support the given op class */ 882147SN/A bool provides(OpClass op_class) { return capabilityList[op_class]; } 892147SN/A}; 902147SN/A 912222SN/A/** Extra timing capability to allow individual ops to have their source 922147SN/A * register dependency latencies tweaked based on the ExtMachInst of the 932147SN/A * source instruction. 942147SN/A */ 952222SN/Aclass MinorFUTiming: public SimObject 962147SN/A{ 972147SN/A public: 982147SN/A /** Mask off the ExtMachInst of an instruction before comparing with 992222SN/A * match */ 1002147SN/A uint64_t mask; 1012147SN/A uint64_t match; 1022147SN/A 1032222SN/A /** Textual description of the decode's purpose */ 1042147SN/A std::string description; 1052147SN/A 1062147SN/A /** If true, instructions matching this mask/match should *not* be 1072222SN/A * issued in this FU */ 1082147SN/A bool suppress; 1092174SN/A 1102174SN/A /** Extra latency that the instruction should spend at the end of 1115569Snate@binkert.org * the pipeline */ 1125569Snate@binkert.org Cycles extraCommitLat; 1132174SN/A TimingExpr *extraCommitLatExpr; 1142680Sktlim@umich.edu 1152222SN/A /** Extra delay that results should show in the scoreboard after 1162174SN/A * leaving the pipeline. If set to Cycles(0) for memory references, 1172196SN/A * an 'unpredictable' return time will be set in the scoreboard 1183521Sgblack@eecs.umich.edu * blocking following dependent instructions from issuing */ 1195568Snate@binkert.org Cycles extraAssumedLat; 1202196SN/A 1212201SN/A /** Cycle offsets from the scoreboard delivery times of register values 1222196SN/A * for each of this instruction's source registers (in srcRegs order). 1235568Snate@binkert.org * The offsets are subtracted from the scoreboard returnCycle times. 1245568Snate@binkert.org * For example, for an instruction type with 3 source registers, 1252196SN/A * [2, 1, 2] will allow the instruction to issue upto 2 cycles early 1262196SN/A * for dependencies on the 1st and 3rd register and upto 1 cycle early 1275568Snate@binkert.org * on the 2nd. */ 1282680Sktlim@umich.edu std::vector<Cycles> srcRegsRelativeLats; 1292174SN/A 1302174SN/A /** Extra opClasses check (after the FU one) */ 1315569Snate@binkert.org MinorOpClassSet *opClasses; 1325569Snate@binkert.org 1332201SN/A public: 1342680Sktlim@umich.edu MinorFUTiming(const MinorFUTimingParams *params); 1352201SN/A 1362201SN/A public: 1372201SN/A /** Does the extra decode in this object support the given op class */ 1385569Snate@binkert.org bool provides(OpClass op_class) { return opClasses->provides(op_class); } 1395569Snate@binkert.org}; 1402289SN/A 1412289SN/A/** A functional unit that can execute any of opClasses operations with a 1422289SN/A * single op(eration)Lat(ency) and issueLat(ency) associated with the unit 1432289SN/A * rather than each operation (as in src/FuncUnit). 1442289SN/A * 1452289SN/A * This is very similar to cpu/func_unit but replicated here to allow 1465569Snate@binkert.org * the Minor functional units to change without having to disturb the common 1475569Snate@binkert.org * definition. 1482289SN/A */ 1495568Snate@binkert.orgclass MinorFU : public SimObject 1502289SN/A{ 1512289SN/A public: 1525568Snate@binkert.org MinorOpClassSet *opClasses; 1535569Snate@binkert.org 1545569Snate@binkert.org /** Delay from issuing the operation, to it reaching the 1555569Snate@binkert.org * end of the associated pipeline */ 1562289SN/A Cycles opLat; 1572289SN/A 1585568Snate@binkert.org /** Delay after issuing an operation before the next 1595568Snate@binkert.org * operation can be issued */ 1602289SN/A Cycles issueLat; 1612289SN/A 1622680Sktlim@umich.edu /** FUs which this pipeline can't receive a forwarded (i.e. relative 1632289SN/A * latency != 0) result from */ 1642289SN/A std::vector<unsigned int> cantForwardFromFUIndices; 1655569Snate@binkert.org 1665569Snate@binkert.org /** Extra timing info to give timings to individual ops */ 1672289SN/A std::vector<MinorFUTiming *> timings; 1682680Sktlim@umich.edu 1695568Snate@binkert.org public: 1705568Snate@binkert.org MinorFU(const MinorFUParams *params) : 1715569Snate@binkert.org SimObject(params), 1722289SN/A opClasses(params->opClasses), 1732289SN/A opLat(params->opLat), 1742680Sktlim@umich.edu issueLat(params->issueLat), 1752289SN/A cantForwardFromFUIndices(params->cantForwardFromFUIndices), 1762289SN/A timings(params->timings) 1774997Sgblack@eecs.umich.edu { } 1784997Sgblack@eecs.umich.edu}; 1795569Snate@binkert.org 1805569Snate@binkert.org/** A collection of MinorFUs */ 1814997Sgblack@eecs.umich.educlass MinorFUPool : public SimObject 1824997Sgblack@eecs.umich.edu{ 1835184Sgblack@eecs.umich.edu public: 1845184Sgblack@eecs.umich.edu std::vector<MinorFU *> funcUnits; 1855569Snate@binkert.org 1864997Sgblack@eecs.umich.edu public: 1874997Sgblack@eecs.umich.edu MinorFUPool(const MinorFUPoolParams *params) : 1884997Sgblack@eecs.umich.edu SimObject(params), 1895004Sgblack@eecs.umich.edu funcUnits(params->funcUnits) 1904997Sgblack@eecs.umich.edu { } 1914997Sgblack@eecs.umich.edu}; 1924997Sgblack@eecs.umich.edu 1935569Snate@binkert.orgnamespace Minor 1945569Snate@binkert.org{ 1954997Sgblack@eecs.umich.edu 1964997Sgblack@eecs.umich.edu/** Container class to box instructions in the FUs to make those 1975184Sgblack@eecs.umich.edu * queues have correct bubble behaviour when stepped */ 1985184Sgblack@eecs.umich.educlass QueuedInst 1995569Snate@binkert.org{ 2004997Sgblack@eecs.umich.edu public: 2015184Sgblack@eecs.umich.edu MinorDynInstPtr inst; 2024997Sgblack@eecs.umich.edu 2035569Snate@binkert.org public: 2044997Sgblack@eecs.umich.edu QueuedInst(MinorDynInstPtr inst_ = MinorDynInst::bubble()) : 2054997Sgblack@eecs.umich.edu inst(inst_) 2065004Sgblack@eecs.umich.edu { } 2074997Sgblack@eecs.umich.edu 2084997Sgblack@eecs.umich.edu public: 2094997Sgblack@eecs.umich.edu /** Report and bubble interfaces */ 2102174SN/A void reportData(std::ostream &os) const; 2112174SN/A bool isBubble() const { return inst->isBubble(); } 2122167SN/A 2132167SN/A static QueuedInst bubble() 214 { return QueuedInst(MinorDynInst::bubble()); } 215}; 216 217/** Functional units have pipelines which stall when an inst gets to 218 * their ends allowing Execute::commit to pick up timing-completed insts 219 * when it feels like it */ 220typedef SelfStallingPipeline<QueuedInst, 221 ReportTraitsAdaptor<QueuedInst> > FUPipelineBase; 222 223/** A functional unit configured from a MinorFU object */ 224class FUPipeline : public FUPipelineBase, public FuncUnit 225{ 226 public: 227 /** Functional unit description that this pipeline implements */ 228 const MinorFU &description; 229 230 /** An FUPipeline needs access to curCycle, use this timing source */ 231 ClockedObject &timeSource; 232 233 /** Set of operation classes supported by this FU */ 234 std::bitset<Num_OpClasses> capabilityList; 235 236 /** FUs which this pipeline can't receive a forwarded (i.e. relative 237 * latency != 0) result from */ 238 std::vector<bool> cantForwardFromFUIndices; 239 240 public: 241 /** When can a new instruction be inserted into the pipeline? This is 242 * an absolute cycle time unless it is 0 in which case the an 243 * instruction can be pushed straightaway */ 244 Cycles nextInsertCycle; 245 246 public: 247 FUPipeline(const std::string &name, const MinorFU &description_, 248 ClockedObject &timeSource_); 249 250 public: 251 /** How many cycles must from curCycle before insertion into the 252 * pipeline is allowed */ 253 Cycles cyclesBeforeInsert(); 254 255 /** Can an instruction be inserted now? */ 256 bool canInsert() const; 257 258 /** Find the extra timing information for this instruction. Returns 259 * NULL if no decode info. is found */ 260 MinorFUTiming *findTiming(const StaticInstPtr &inst); 261 262 /** Step the pipeline. Allow multiple steps? */ 263 void advance(); 264}; 265 266} 267 268#endif /* __CPU_MINOR_FUNC_UNIT_HH__ */ 269