Searched refs:numThreads (Results 1 - 25 of 53) sorted by relevance

123

/gem5/src/cpu/o3/
H A Dderiv.cc45 if (workload.size() > numThreads) {
47 workload.size(), numThreads);
55 (numThreads >= workload.size()) ? numThreads : workload.size();
58 numThreads = actual_num_threads;
H A Drob_impl.hh64 numThreads(params->numThreads)
69 for (ThreadID tid = 0; tid < numThreads; tid++) {
77 int part_amt = numEntries / numThreads;
80 for (ThreadID tid = 0; tid < numThreads; tid++) {
90 for (ThreadID tid = 0; tid < numThreads; tid++) {
95 for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
139 for (ThreadID tid = 0; tid < numThreads; tid++)
155 if (robPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) {
191 for (ThreadID tid = 0; tid < numThreads; ti
[all...]
H A Dcommit_impl.hh93 numThreads(params->numThreads),
110 for (ThreadID tid = 0; tid < numThreads; tid++) {
177 .init(cpu->numThreads)
184 .init(cpu->numThreads)
191 .init(cpu->numThreads)
198 .init(cpu->numThreads)
205 .init(cpu->numThreads)
212 .init(cpu->numThreads)
219 .init(cpu->numThreads)
[all...]
H A Dcpu.cc129 isa(numThreads, NULL),
160 thread.resize(numThreads);
161 tids.resize(numThreads);
212 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
213 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
214 assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
215 assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs);
216 assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
222 for (ThreadID tid = 0; tid < numThreads; tid++) {
309 this->thread.resize(this->numThreads);
[all...]
H A Dinst_queue_impl.hh100 numThreads = params->numThreads;
128 for (ThreadID tid = 0; tid < numThreads; tid++) {
134 int part_amt = numEntries / numThreads;
137 for (ThreadID tid = 0; tid < numThreads; tid++) {
149 for (ThreadID tid = 0; tid < numThreads; tid++) {
156 for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) {
273 .init(numThreads,Enums::Num_OpClass)
315 .init(numThreads)
328 for (ThreadID tid = 0; tid < numThreads; ti
[all...]
H A Dlsq_impl.hh71 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
73 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
76 numThreads(params->numThreads)
78 assert(numThreads > 0 && numThreads <= Impl::MaxThreads);
104 thread.reserve(numThreads);
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
125 for (ThreadID tid = 0; tid < numThreads; tid++) {
144 for (ThreadID tid = 0; tid < numThreads; ti
[all...]
H A DO3CPU.py176 branchPred = Param.BranchPredictor(TournamentBP(numThreads =
177 Parent.numThreads),
H A Dfetch_impl.hh99 numThreads(params->numThreads),
104 if (numThreads > Impl::MaxThreads)
105 fatal("numThreads (%d) is larger than compiled limit (%d),\n"
107 numThreads, static_cast<int>(Impl::MaxThreads));
120 panic_if(fetchPolicy == FetchPolicy::SingleThread && numThreads > 1,
144 for (ThreadID tid = 0; tid < numThreads; tid++) {
363 for (ThreadID tid = 0; tid < numThreads; ++tid) {
435 for (ThreadID i = 0; i < numThreads; ++i) {
451 for (ThreadID i = 0; i < numThreads;
[all...]
H A Diew_impl.hh82 numThreads(params->numThreads)
220 .init(cpu->numThreads)
230 .init(cpu->numThreads)
236 .init(cpu->numThreads)
242 .init(cpu->numThreads)
248 .init(cpu->numThreads)
267 .init(cpu->numThreads)
273 .init(cpu->numThreads)
279 .init(cpu->numThreads)
[all...]
/gem5/src/cpu/simple/
H A Dnoncaching.cc70 numThreads = 1;
H A Datomic.cc134 for (ThreadID tid = 0; tid < numThreads; tid++) {
160 for (ThreadID tid = 0; tid < numThreads; tid++) {
230 assert(thread_num < numThreads);
256 assert(thread_num < numThreads);
292 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
321 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
641 if (numThreads > 1) {
/gem5/src/cpu/
H A Dbase.cc135 numThreads(p->numThreads), system(p->system),
139 addressMonitor(p->numThreads),
156 if (numThreads > maxThreadsPerCPU)
157 maxThreadsPerCPU = numThreads;
160 comInstEventQueue = new EventQueue *[numThreads];
161 for (ThreadID tid = 0; tid < numThreads; ++tid)
170 for (ThreadID tid = 0; tid < numThreads; ++tid)
191 *counter = numThreads;
192 for (ThreadID tid = 0; tid < numThreads;
[all...]
H A DBaseCPU.py155 numThreads = Param.Unsigned(1, "number of HW thread contexts") variable in class:BaseCPU
227 self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
281 self.isa = [ ArchISA() for i in range(self.numThreads) ]
283 if len(self.isa) != int(self.numThreads):
315 for i in range(int(self.numThreads)):
/gem5/configs/example/
H A Detrace_replay.py69 numThreads = 1 variable
81 CPUClass.numThreads = numThreads
H A Dse.py136 numThreads = 1 variable
162 multiprocesses, numThreads = get_processes(options)
169 CPUClass.numThreads = numThreads
181 if numThreads > 1:
/gem5/src/cpu/minor/
H A Dcpu.hh172 for (ThreadID i = 1; i <= numThreads; i++) {
173 prio_list.push_back((priority + i) % numThreads);
181 for (ThreadID i = 0; i < numThreads; i++) {
H A Dstats.cc87 .init(baseCpu.numThreads, Enums::Num_OpClass)
H A Ddecode.cc61 decodeInfo(params.numThreads),
73 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
134 for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
283 for (ThreadID i = 0; i < cpu.numThreads; i++)
H A Dcpu.cc57 for (ThreadID i = 0; i < numThreads; i++) {
172 assert(tid < numThreads);
186 for (ThreadID tid = 0; tid < numThreads; tid++) {
243 for (ThreadID tid = 0; tid < numThreads; tid++){
H A DMinorCPU.py288 numThreads = Parent.numThreads), "Branch Predictor")
/gem5/src/cpu/pred/
H A Dbtb.hh69 unsigned instShiftAmt, unsigned numThreads);
H A DBranchPredictor.py40 numThreads = Param.Unsigned(Parent.numThreads, "Number of threads") variable in class:IndirectPredictor
63 numThreads = Param.Unsigned(Parent.numThreads, "Number of threads") variable in class:BranchPredictor
110 numThreads = Param.Unsigned(Parent.numThreads, "Number of threads") variable in class:TAGEBase
H A Dbpred_unit.cc58 numThreads(params->numThreads),
59 predHist(numThreads),
63 params->numThreads),
64 RAS(numThreads),
/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py98 numThreads = Param.Unsigned(1, "number of HW thread contexts") variable in class:BaseTrafficGen
/gem5/src/arch/mips/
H A Disa.hh62 uint8_t numThreads; member in class:MipsISA::ISA

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