13760SN/A/*
23760SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
33760SN/A * All rights reserved.
43760SN/A *
53760SN/A * Redistribution and use in source and binary forms, with or without
63760SN/A * modification, are permitted provided that the following conditions are
73760SN/A * met: redistributions of source code must retain the above copyright
83760SN/A * notice, this list of conditions and the following disclaimer;
93760SN/A * redistributions in binary form must reproduce the above copyright
103760SN/A * notice, this list of conditions and the following disclaimer in the
113760SN/A * documentation and/or other materials provided with the distribution;
123760SN/A * neither the name of the copyright holders nor the names of its
133760SN/A * contributors may be used to endorse or promote products derived from
143760SN/A * this software without specific prior written permission.
153760SN/A *
163760SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
173760SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
183760SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
193760SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
203760SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
213760SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
223760SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
233760SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
243760SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
253760SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
263760SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
273760SN/A *
285597SN/A * Authors: Kevin Lim
293760SN/A */
303760SN/A
3111793Sbrandon.potter@amd.com#include "cpu/o3/deriv.hh"
3211793Sbrandon.potter@amd.com
333760SN/A#include <string>
343760SN/A
354762SN/A#include "params/DerivO3CPU.hh"
363760SN/A
374762SN/ADerivO3CPU *
384762SN/ADerivO3CPUParams::create()
393760SN/A{
408793SN/A    ThreadID actual_num_threads;
418793SN/A    if (FullSystem) {
428793SN/A        // Full-system only supports a single thread for the moment.
438793SN/A        actual_num_threads = 1;
448793SN/A    } else {
458793SN/A        if (workload.size() > numThreads) {
468793SN/A            fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
478793SN/A                  workload.size(), numThreads);
488793SN/A        } else if (workload.size() == 0) {
498793SN/A            fatal("Must specify at least one workload!");
508793SN/A        }
518793SN/A
528793SN/A        // In non-full-system mode, we infer the number of threads from
538793SN/A        // the workload if it's not explicitly specified.
548793SN/A        actual_num_threads =
558793SN/A            (numThreads >= workload.size()) ? numThreads : workload.size();
566387SN/A    }
573760SN/A
585529SN/A    numThreads = actual_num_threads;
593760SN/A
6013559Snikos.nikoleris@arm.com    if (actual_num_threads > 1 && smtFetchPolicy == FetchPolicy::SingleThread)
6113559Snikos.nikoleris@arm.com        smtFetchPolicy = FetchPolicy::RoundRobin;
623760SN/A
635529SN/A    return new DerivO3CPU(this);
643760SN/A}
65