Searched refs:getITBPtr (Results 1 - 21 of 21) sorted by relevance

/gem5/src/arch/arm/
H A Dtlbi_op.cc50 getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
56 getITBPtr(checker)->flushAllSecurity(secureLookup,
66 getITBPtr(tc)->flushAllSecurity(secureLookup, targetEL);
78 getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
82 getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL);
90 getITBPtr(tc)->flushAsid(asid, secureLookup, targetEL);
102 getITBPtr(tc)->flushAllNs(targetEL);
107 getITBPtr(checker)->flushAllNs(targetEL);
115 getITBPtr(tc)->flushMva(addr, secureLookup, targetEL);
120 getITBPtr(checke
[all...]
H A Dvtophys.cc88 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
H A Dtlb.hh468 getITBPtr(T *tc) function in namespace:ArmISA
470 auto tlb = static_cast<TLB *>(tc->getITBPtr());
H A Disa.cc790 getITBPtr(tc)->invalidateMiscReg();
1051 getITBPtr(tc)->invalidateMiscReg();
1070 getITBPtr(tc)->invalidateMiscReg();
1817 getITBPtr(tc)->invalidateMiscReg();
1834 getITBPtr(tc)->invalidateMiscReg();
1859 getITBPtr(tc)->invalidateMiscReg();
H A Dutility.cc191 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
/gem5/src/arch/alpha/
H A Dev5.cc48 getITBPtr(T *tc) function in namespace:AlphaISA
50 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
444 getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry);
452 getITBPtr(tc)->flushAll();
459 getITBPtr(tc)->flushProcesses();
466 getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
H A Dfaults.cc206 dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
/gem5/src/cpu/
H A Dbase.cc625 Port *old_itb_port = oldTC->getITBPtr()->getTableWalkerPort();
627 Port *new_itb_port = newTC->getITBPtr()->getTableWalkerPort();
635 newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
644 oldChecker->getITBPtr()->getTableWalkerPort();
648 newChecker->getITBPtr()->getTableWalkerPort();
652 newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
692 tc.getITBPtr()->flushAll();
695 checker->getITBPtr()
[all...]
H A Dthread_context.hh137 virtual BaseTLB *getITBPtr() = 0;
H A Dsimple_thread.hh200 BaseTLB *getITBPtr() override { return itb; }
/gem5/src/arch/sparc/
H A Dvtophys.cc86 TLB* itb = dynamic_cast<TLB *>(tc->getITBPtr());
H A Dtlb.cc870 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1066 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1303 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
H A Dfaults.cc675 dynamic_cast<TLB *>(tc->getITBPtr())->
/gem5/src/arch/x86/
H A Disa.cc219 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
236 dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
243 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
H A Dfaults.cc141 tc->getITBPtr()->demapPage(addr, 0);
H A Dutility.cc230 dest->getITBPtr()->flushAll();
/gem5/src/cpu/checker/
H A Dthread_context.hh117 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
H A Dcpu.hh160 BaseTLB* getITBPtr() { return itb; } function in class:CheckerCPU
/gem5/src/cpu/minor/
H A Dexec_context.hh411 thread.getITBPtr()->demapPage(vaddr, asn);
434 thread.getITBPtr()->demapPage(vaddr, asn);
/gem5/src/cpu/o3/
H A Dthread_context.hh82 BaseTLB *getITBPtr() override { return cpu->itb; }
/gem5/src/sim/
H A Dsyscall_emul.hh1840 tc->getITBPtr()->flushAll();

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