1/*
2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
45#define __CPU_CHECKER_THREAD_CONTEXT_HH__
46
47#include "arch/types.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/simple_thread.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Checker.hh"
53
54class EndQuiesceEvent;
55namespace Kernel {
56    class Statistics;
57};
58namespace TheISA {
59    class Decoder;
60};
61
62/**
63 * Derived ThreadContext class for use with the Checker.  The template
64 * parameter is the ThreadContext class used by the specific CPU being
65 * verified.  This CheckerThreadContext is then used by the main CPU
66 * in place of its usual ThreadContext class.  It handles updating the
67 * checker's state any time state is updated externally through the
68 * ThreadContext.
69 */
70template <class TC>
71class CheckerThreadContext : public ThreadContext
72{
73  public:
74    CheckerThreadContext(TC *actual_tc,
75                         CheckerCPU *checker_cpu)
76        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
77          checkerCPU(checker_cpu)
78    { }
79
80  private:
81    /** The main CPU's ThreadContext, or class that implements the
82     * ThreadContext interface. */
83    TC *actualTC;
84    /** The checker's own SimpleThread. Will be updated any time
85     * anything uses this ThreadContext to externally update a
86     * thread's state. */
87    SimpleThread *checkerTC;
88    /** Pointer to the checker CPU. */
89    CheckerCPU *checkerCPU;
90
91  public:
92
93    BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
94
95    uint32_t socketId() const override { return actualTC->socketId(); }
96
97    int cpuId() const override { return actualTC->cpuId(); }
98
99    ContextID contextId() const override { return actualTC->contextId(); }
100
101    void
102    setContextId(ContextID id) override
103    {
104       actualTC->setContextId(id);
105       checkerTC->setContextId(id);
106    }
107
108    /** Returns this thread's ID number. */
109    int threadId() const override { return actualTC->threadId(); }
110    void
111    setThreadId(int id) override
112    {
113        checkerTC->setThreadId(id);
114        actualTC->setThreadId(id);
115    }
116
117    BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
118
119    BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
120
121    CheckerCPU *
122    getCheckerCpuPtr() override
123    {
124        return checkerCPU;
125    }
126
127    TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
128
129    TheISA::Decoder *
130    getDecoderPtr() override
131    {
132        return actualTC->getDecoderPtr();
133    }
134
135    System *getSystemPtr() override { return actualTC->getSystemPtr(); }
136
137    ::Kernel::Statistics *
138    getKernelStats() override
139    {
140        return actualTC->getKernelStats();
141    }
142
143    Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
144
145    void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
146
147    PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
148
149    PortProxy &
150    getVirtProxy() override
151    {
152        return actualTC->getVirtProxy();
153    }
154
155    void
156    initMemProxies(ThreadContext *tc) override
157    {
158        actualTC->initMemProxies(tc);
159    }
160
161    void
162    connectMemPorts(ThreadContext *tc)
163    {
164        actualTC->connectMemPorts(tc);
165    }
166
167    /** Executes a syscall in SE mode. */
168    void
169    syscall(int64_t callnum, Fault *fault) override
170    {
171        return actualTC->syscall(callnum, fault);
172    }
173
174    Status status() const override { return actualTC->status(); }
175
176    void
177    setStatus(Status new_status) override
178    {
179        actualTC->setStatus(new_status);
180        checkerTC->setStatus(new_status);
181    }
182
183    /// Set the status to Active.
184    void activate() override { actualTC->activate(); }
185
186    /// Set the status to Suspended.
187    void suspend() override { actualTC->suspend(); }
188
189    /// Set the status to Halted.
190    void halt() override { actualTC->halt(); }
191
192    void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
193
194    void
195    takeOverFrom(ThreadContext *oldContext) override
196    {
197        actualTC->takeOverFrom(oldContext);
198        checkerTC->copyState(oldContext);
199    }
200
201    void
202    regStats(const std::string &name) override
203    {
204        actualTC->regStats(name);
205        checkerTC->regStats(name);
206    }
207
208    EndQuiesceEvent *
209    getQuiesceEvent() override
210    {
211        return actualTC->getQuiesceEvent();
212    }
213
214    Tick readLastActivate() override { return actualTC->readLastActivate(); }
215    Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
216
217    void profileClear() override { return actualTC->profileClear(); }
218    void profileSample() override { return actualTC->profileSample(); }
219
220    // @todo: Do I need this?
221    void
222    copyArchRegs(ThreadContext *tc) override
223    {
224        actualTC->copyArchRegs(tc);
225        checkerTC->copyArchRegs(tc);
226    }
227
228    void
229    clearArchRegs() override
230    {
231        actualTC->clearArchRegs();
232        checkerTC->clearArchRegs();
233    }
234
235    //
236    // New accessors for new decoder.
237    //
238    RegVal
239    readIntReg(RegIndex reg_idx) const override
240    {
241        return actualTC->readIntReg(reg_idx);
242    }
243
244    RegVal
245    readFloatReg(RegIndex reg_idx) const override
246    {
247        return actualTC->readFloatReg(reg_idx);
248    }
249
250    const VecRegContainer &
251    readVecReg (const RegId &reg) const override
252    {
253        return actualTC->readVecReg(reg);
254    }
255
256    /**
257     * Read vector register for modification, hierarchical indexing.
258     */
259    VecRegContainer &
260    getWritableVecReg (const RegId &reg) override
261    {
262        return actualTC->getWritableVecReg(reg);
263    }
264
265    /** Vector Register Lane Interfaces. */
266    /** @{ */
267    /** Reads source vector 8bit operand. */
268    ConstVecLane8
269    readVec8BitLaneReg(const RegId &reg) const override
270    {
271        return actualTC->readVec8BitLaneReg(reg);
272    }
273
274    /** Reads source vector 16bit operand. */
275    ConstVecLane16
276    readVec16BitLaneReg(const RegId &reg) const override
277    {
278        return actualTC->readVec16BitLaneReg(reg);
279    }
280
281    /** Reads source vector 32bit operand. */
282    ConstVecLane32
283    readVec32BitLaneReg(const RegId &reg) const override
284    {
285        return actualTC->readVec32BitLaneReg(reg);
286    }
287
288    /** Reads source vector 64bit operand. */
289    ConstVecLane64
290    readVec64BitLaneReg(const RegId &reg) const override
291    {
292        return actualTC->readVec64BitLaneReg(reg);
293    }
294
295    /** Write a lane of the destination vector register. */
296    virtual void
297    setVecLane(const RegId &reg,
298               const LaneData<LaneSize::Byte> &val) override
299    {
300        return actualTC->setVecLane(reg, val);
301    }
302    virtual void
303    setVecLane(const RegId &reg,
304               const LaneData<LaneSize::TwoByte> &val) override
305    {
306        return actualTC->setVecLane(reg, val);
307    }
308    virtual void
309    setVecLane(const RegId &reg,
310               const LaneData<LaneSize::FourByte> &val) override
311    {
312        return actualTC->setVecLane(reg, val);
313    }
314    virtual void
315    setVecLane(const RegId &reg,
316               const LaneData<LaneSize::EightByte> &val) override
317    {
318        return actualTC->setVecLane(reg, val);
319    }
320    /** @} */
321
322    const VecElem &
323    readVecElem(const RegId& reg) const override
324    {
325        return actualTC->readVecElem(reg);
326    }
327
328    const VecPredRegContainer &
329    readVecPredReg(const RegId& reg) const override
330    {
331        return actualTC->readVecPredReg(reg);
332    }
333
334    VecPredRegContainer &
335    getWritableVecPredReg(const RegId& reg) override
336    {
337        return actualTC->getWritableVecPredReg(reg);
338    }
339
340    RegVal
341    readCCReg(RegIndex reg_idx) const override
342    {
343        return actualTC->readCCReg(reg_idx);
344    }
345
346    void
347    setIntReg(RegIndex reg_idx, RegVal val) override
348    {
349        actualTC->setIntReg(reg_idx, val);
350        checkerTC->setIntReg(reg_idx, val);
351    }
352
353    void
354    setFloatReg(RegIndex reg_idx, RegVal val) override
355    {
356        actualTC->setFloatReg(reg_idx, val);
357        checkerTC->setFloatReg(reg_idx, val);
358    }
359
360    void
361    setVecReg(const RegId& reg, const VecRegContainer& val) override
362    {
363        actualTC->setVecReg(reg, val);
364        checkerTC->setVecReg(reg, val);
365    }
366
367    void
368    setVecElem(const RegId& reg, const VecElem& val) override
369    {
370        actualTC->setVecElem(reg, val);
371        checkerTC->setVecElem(reg, val);
372    }
373
374    void
375    setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
376    {
377        actualTC->setVecPredReg(reg, val);
378        checkerTC->setVecPredReg(reg, val);
379    }
380
381    void
382    setCCReg(RegIndex reg_idx, RegVal val) override
383    {
384        actualTC->setCCReg(reg_idx, val);
385        checkerTC->setCCReg(reg_idx, val);
386    }
387
388    /** Reads this thread's PC state. */
389    TheISA::PCState pcState() const override { return actualTC->pcState(); }
390
391    /** Sets this thread's PC state. */
392    void
393    pcState(const TheISA::PCState &val) override
394    {
395        DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
396                         val, checkerTC->pcState());
397        checkerTC->pcState(val);
398        checkerCPU->recordPCChange(val);
399        return actualTC->pcState(val);
400    }
401
402    void
403    setNPC(Addr val)
404    {
405        checkerTC->setNPC(val);
406        actualTC->setNPC(val);
407    }
408
409    void
410    pcStateNoRecord(const TheISA::PCState &val) override
411    {
412        return actualTC->pcState(val);
413    }
414
415    /** Reads this thread's PC. */
416    Addr instAddr() const override { return actualTC->instAddr(); }
417
418    /** Reads this thread's next PC. */
419    Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
420
421    /** Reads this thread's next PC. */
422    MicroPC microPC() const override { return actualTC->microPC(); }
423
424    RegVal
425    readMiscRegNoEffect(RegIndex misc_reg) const override
426    {
427        return actualTC->readMiscRegNoEffect(misc_reg);
428    }
429
430    RegVal
431    readMiscReg(RegIndex misc_reg) override
432    {
433        return actualTC->readMiscReg(misc_reg);
434    }
435
436    void
437    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
438    {
439        DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
440                         " and O3..\n", misc_reg);
441        checkerTC->setMiscRegNoEffect(misc_reg, val);
442        actualTC->setMiscRegNoEffect(misc_reg, val);
443    }
444
445    void
446    setMiscReg(RegIndex misc_reg, RegVal val) override
447    {
448        DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
449                         " and O3..\n", misc_reg);
450        checkerTC->setMiscReg(misc_reg, val);
451        actualTC->setMiscReg(misc_reg, val);
452    }
453
454    RegId
455    flattenRegId(const RegId& regId) const override
456    {
457        return actualTC->flattenRegId(regId);
458    }
459
460    unsigned
461    readStCondFailures() const override
462    {
463        return actualTC->readStCondFailures();
464    }
465
466    void
467    setStCondFailures(unsigned sc_failures) override
468    {
469        actualTC->setStCondFailures(sc_failures);
470    }
471
472    Counter
473    readFuncExeInst() const override
474    {
475        return actualTC->readFuncExeInst();
476    }
477
478    RegVal
479    readIntRegFlat(RegIndex idx) const override
480    {
481        return actualTC->readIntRegFlat(idx);
482    }
483
484    void
485    setIntRegFlat(RegIndex idx, RegVal val) override
486    {
487        actualTC->setIntRegFlat(idx, val);
488    }
489
490    RegVal
491    readFloatRegFlat(RegIndex idx) const override
492    {
493        return actualTC->readFloatRegFlat(idx);
494    }
495
496    void
497    setFloatRegFlat(RegIndex idx, RegVal val) override
498    {
499        actualTC->setFloatRegFlat(idx, val);
500    }
501
502    const VecRegContainer &
503    readVecRegFlat(RegIndex idx) const override
504    {
505        return actualTC->readVecRegFlat(idx);
506    }
507
508    /**
509     * Read vector register for modification, flat indexing.
510     */
511    VecRegContainer &
512    getWritableVecRegFlat(RegIndex idx) override
513    {
514        return actualTC->getWritableVecRegFlat(idx);
515    }
516
517    void
518    setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
519    {
520        actualTC->setVecRegFlat(idx, val);
521    }
522
523    const VecElem &
524    readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
525    {
526        return actualTC->readVecElemFlat(idx, elem_idx);
527    }
528
529    void
530    setVecElemFlat(RegIndex idx,
531                   const ElemIndex& elem_idx, const VecElem& val) override
532    {
533        actualTC->setVecElemFlat(idx, elem_idx, val);
534    }
535
536    const VecPredRegContainer &
537    readVecPredRegFlat(RegIndex idx) const override
538    {
539        return actualTC->readVecPredRegFlat(idx);
540    }
541
542    VecPredRegContainer &
543    getWritableVecPredRegFlat(RegIndex idx) override
544    {
545        return actualTC->getWritableVecPredRegFlat(idx);
546    }
547
548    void
549    setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
550    {
551        actualTC->setVecPredRegFlat(idx, val);
552    }
553
554    RegVal
555    readCCRegFlat(RegIndex idx) const override
556    {
557        return actualTC->readCCRegFlat(idx);
558    }
559
560    void
561    setCCRegFlat(RegIndex idx, RegVal val) override
562    {
563        actualTC->setCCRegFlat(idx, val);
564    }
565};
566
567#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
568