| /gem5/system/arm/dt/ |
| H A D | Makefile | 36 CREATE_TARGET=$(foreach n, $(NUM_CPUS), $(1)_$(n)cpu.dtb)
45 armv8_gem5_v1_big_little_2_2.dtb \
46 armv8_gem5_v1_big_little_2_4.dtb
78 %.dtb: .gen/%.dts
79 $(DTC) -I dts -O dtb -o $@ $<
84 $(RM) *.dtb
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| /gem5/util/tlm/ |
| H A D | run_gem5_fs.sh | 48 --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
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| /gem5/src/cpu/simple/ |
| H A D | BaseSimpleCPU.py | 49 self.checker.dtb = ArmTLB(size = self.dtb.size)
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| H A D | timing.cc | 461 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
462 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
468 thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
550 thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
551 thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
557 thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
608 thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
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| H A D | atomic.cc | 401 fault = thread->dtb->translateAtomic(req, thread->getTC(),
492 fault = thread->dtb->translateAtomic(req, thread->getTC(),
602 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
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| /gem5/src/arch/sparc/ |
| H A D | vtophys.cc | 87 TLB* dtb = dynamic_cast<TLB *>(tc->getDTBPtr()); local
100 tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context ,
111 dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
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| /gem5/util/dist/test/ |
| H A D | test-2nodes-AArch64.sh | 52 DTB=$M5_PATH/binaries/vexpress.aarch64.20140821.dtb
78 --dtb-filename=$DTB \
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record_v8.cc | 59 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr()); local
60 paddrValid = dtb->translateFunctional(thread, addr, paddr);
73 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr()); local
74 dtb->translateFunctional(thread, addr, paddr);
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| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 88 dtb = p->dtb;
106 thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
111 itb, dtb, p->isa[0]);
201 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
285 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
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| H A D | cpu.hh | 138 BaseTLB *dtb; member in class:CheckerCPU
161 BaseTLB* getDTBPtr() { return dtb; }
513 this->dtb->demapPage(vaddr, asn);
520 { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
533 this->dtb->demapPage(vaddr, asn);
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| /gem5/src/arch/arm/ |
| H A D | ArmPMU.py | 103 itb=None, dtb=None,
127 self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
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| H A D | ArmTLB.py | 97 # We rely on the dtb being a parameter of the CPU, and get the
99 tlb = Parent.dtb
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| /gem5/configs/example/arm/ |
| H A D | starter_fs.py | 151 if args.dtb:
152 system.dtb_filename = args.dtb
155 system.generateDtb(m5.options.outdir, 'system.dtb')
201 parser.add_argument("--dtb", type=str, default=None,
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| H A D | fs_bigLITTLE.py | 162 parser.add_argument("--dtb", type=str, default=None,
273 if options.dtb is not None:
274 system.dtb_filename = SysPaths.binary(options.dtb)
276 system.generateDtb(m5.options.outdir, 'system.dtb')
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| /gem5/src/cpu/o3/ |
| H A D | O3CPU.py | 191 self.checker.dtb = ArmTLB(size = self.dtb.size)
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| H A D | cpu.hh | 128 BaseTLB *dtb; member in class:FullO3CPU
203 this->dtb->demapPage(vaddr, asn);
213 this->dtb->demapPage(vaddr, asn);
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| /gem5/src/cpu/ |
| H A D | simple_thread.cc | 81 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
92 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
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| H A D | simple_thread.hh | 132 BaseTLB *dtb; member in class:SimpleThread
172 dtb->demapPage(vaddr, asn);
182 dtb->demapPage(vaddr, asn);
202 BaseTLB *getDTBPtr() override { return dtb; }
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| H A D | BaseCPU.py | 183 dtb = Param.BaseTLB(ArchDTB(), "Data TLB") variable in class:BaseCPU
217 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
256 self.dtb.walker.port = dwc.cpu_side
260 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
266 "checker.dtb.walker.port"]
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| H A D | base.hh | 642 void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
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| /gem5/tests/configs/ |
| H A D | pc-simple-timing-ruby.py | 86 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
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| /gem5/src/cpu/minor/ |
| H A D | cpu.cc | 60 params->itb, params->dtb, params->isa[i]);
64 params->workload[i], params->itb, params->dtb,
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| /gem5/configs/learning_gem5/part3/ |
| H A D | msi_caches.py | 119 cpu.dtb.walker.port = self.sequencers[i].slave
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| H A D | ruby_caches_MI_example.py | 117 cpu.dtb.walker.port = self.sequencers[i].slave
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| /gem5/configs/example/ |
| H A D | se.py | 271 system.cpu[i].dtb.walker.port = ruby_port.slave
|