Searched refs:cpsr (Results 1 - 25 of 26) sorted by relevance

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/gem5/src/arch/arm/
H A Dinterrupts.hh143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
147 bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
148 bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
149 bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
176 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const argument
186 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
191 getISR(HCR hcr, CPSR cpsr, SCR scr) argument
196 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
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H A Dutility.hh121 inUserMode(CPSR cpsr) argument
123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
133 inPrivilegedMode(CPSR cpsr) argument
135 return !inUserMode(cpsr);
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
150 return (OperatingMode) (uint8_t) cpsr.mode;
160 currEL(CPSR cpsr) argument
162 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
237 inSecureState(SCR scr, CPSR cpsr) argument
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H A Dfaults.cc301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
302 assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
303 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
305 switch (cpsr.mode)
426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
429 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
525 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
526 cpsr.mode = toMode;
529 if (cpsr.mode == MODE_HYP) {
531 cpsr
644 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
730 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
757 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
800 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
849 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
872 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
943 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
1014 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
1077 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
1286 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
1347 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
1449 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
1488 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
1536 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); local
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H A Disa.cc217 CPSR cpsr = 0; local
218 cpsr.mode = MODE_USER;
224 miscRegs[MISCREG_CPSR] = cpsr;
225 updateRegMap(cpsr);
269 CPSR cpsr = 0; local
276 cpsr.mode = MODE_EL3H;
280 cpsr.mode = MODE_EL2H;
284 cpsr.mode = MODE_EL1H;
293 cpsr.daif = 0xf; // Mask all interrupts
294 cpsr
623 CPSR cpsr = 0; variable
631 CPSR cpsr = 0; variable
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H A Dinterrupts.cc57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
73 cpsr_mask_bit = cpsr.f;
79 cpsr_mask_bit = cpsr.i;
85 cpsr_mask_bit = cpsr.a;
H A Dremote_gdb.hh75 uint32_t cpsr; member in struct:ArmISA::RemoteGDB::AArch32GdbRegCache::__anon1
99 uint32_t cpsr; member in struct:ArmISA::RemoteGDB::AArch64GdbRegCache::__anon2
H A Dutility.cc214 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
215 return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
340 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
343 aarch32 = (cpsr.width == 1);
472 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
479 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, argument
613 if (!inSecureState(scr, cpsr) && (cpsr
652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, HCR hcr, uint32_t iss) argument
700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) argument
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H A Dnativetrace.cc58 "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
119 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
120 cpsr.nz = tc->readCCReg(CCREG_NZ);
121 cpsr.c = tc->readCCReg(CCREG_C);
122 cpsr.v = tc->readCCReg(CCREG_V);
123 cpsr.ge = tc->readCCReg(CCREG_GE);
125 newState[STATE_CPSR] = cpsr;
H A Disa.hh381 updateRegMap(CPSR cpsr) argument
383 if (cpsr.width == 0) {
386 switch (cpsr.mode) {
424 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
425 assert(cpsr.width);
429 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
430 assert(!cpsr.width);
481 CPSR cpsr = miscRegs[MISCREG_CPSR]; local
483 (OperatingMode) (uint8_t) cpsr.mode);
484 if (!cpsr
546 CPSR cpsr = miscRegs[MISCREG_CPSR]; local
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H A Dremote_gdb.cc210 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
234 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
274 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
310 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
H A Dmiscregs.hh1003 "cpsr",
1909 CPSR cpsr);
1925 CPSR cpsr);
1928 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1932 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
H A Dtlb.hh148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
411 CPSR cpsr; member in class:ArmISA::TLB
H A Dprocess.cc130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
131 cpsr.mode = MODE_EL0T;
132 tc->setMiscReg(MISCREG_CPSR, cpsr);
H A Dpmu.cc501 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
502 const ExceptionLevel el(currEL(cpsr));
503 const bool secure(inSecureState(scr, cpsr));
H A Dtlb.cc1026 if (mmfr1.pan && cpsr.pan && (ap & 0x1) && mode != Execute &&
1304 cpsr = tc->readMiscReg(MISCREG_CPSR);
1310 aarch64EL = tranTypeEL(cpsr, tranType);
1373 isPriv = cpsr.mode != MODE_USER;
1395 isHyp = cpsr.mode == MODE_HYP;
1423 TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type) argument
1444 return currEL(cpsr);
H A Dmiscregs.cc989 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) argument
995 switch (cpsr.mode) {
1025 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) argument
1031 switch (cpsr.mode) {
1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument
1138 switch (currEL(cpsr)) {
1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument
1161 ExceptionLevel el = currEL(cpsr);
H A Dtable_walker.hh732 /** Cached copy of the cpsr as it existed when translation began */
733 CPSR cpsr; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc221 CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
222 cpsr.nz = tc->readCCReg(CCREG_NZ);
223 cpsr.c = tc->readCCReg(CCREG_C);
224 cpsr.v = tc->readCCReg(CCREG_V);
225 if (cpsr.width) {
226 cpsr.ge = tc->readCCReg(CCREG_GE);
228 cpsr.ge = 0;
230 DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
231 setOneReg(INT_REG(regs.pstate), static_cast<uint64_t>(cpsr));
287 const CPSR cpsr(getOneRegU6
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/gem5/src/arch/arm/tracers/
H A Dtarmac_record.cc204 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR); local
205 cpsr.nz = thread->readCCReg(CCREG_NZ);
206 cpsr.c = thread->readCCReg(CCREG_C);
207 cpsr.v = thread->readCCReg(CCREG_V);
208 cpsr.ge = thread->readCCReg(CCREG_GE);
211 valueLo = cpsr;
252 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR); local
253 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
H A Dtarmac_base.cc76 const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR); local
77 mode = (OperatingMode) (uint8_t)cpsr.mode;
H A Dtarmac_parser.cc76 { "cpsr", MISCREG_CPSR },
685 CPSR cpsr = thread->readMiscRegNoEffect(it->index); local
686 cpsr.nz = thread->readCCReg(CCREG_NZ);
687 cpsr.c = thread->readCCReg(CCREG_C);
688 cpsr.v = thread->readCCReg(CCREG_V);
689 cpsr.ge = thread->readCCReg(CCREG_GE);
690 value_lo = cpsr;
692 CPSR cpsr = 0; local
693 cpsr.nz = thread->readCCReg(CCREG_NZ);
694 cpsr
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/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, argument
206 bool privileged = (cpsr.mode != MODE_USER);
209 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity;
235 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
277 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
402 Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const;
412 CPSR cpsr, CPACR cpacr) const;
421 CPSR cpsr, CPACR cpacr,
446 Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const;
454 Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) cons
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H A Dstatic_inst.cc668 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
687 CPSR cpsr, CPACR cpacr) const
694 return checkFPAdvSIMDTrap64(tc, cpsr);
699 CPSR cpsr, CPACR cpacr,
709 return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
736 return checkFPAdvSIMDTrap64(tc, cpsr);
875 CPSR cpsr, SCR scr,
886 ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) &&
901 ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
989 ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) cons
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H A Dmisc64.cc149 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
154 if (!inSecureState(scr, cpsr) && (el != EL2)) {
377 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); local
378 const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2331 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); local
2333 return ArmISA::inSecureState(scr, cpsr);
2339 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); local
2340 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2343 return (ExceptionLevel)(uint8_t) cpsr.el;
2345 switch (cpsr.mode) {
2391 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); local
2392 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2399 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); local
2400 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr
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