arch/arm/faults.cc

301     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
302     assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
303     assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
305     switch (cpsr.mode)
426     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
429     fromMode = (OperatingMode) (uint8_t) cpsr.mode;
525     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
526     cpsr.mode = toMode;
529     if (cpsr.mode == MODE_HYP) {
531         cpsr.t = hsctlr.te;
532         cpsr.e = hsctlr.ee;
533         if (!scr.ea)  {cpsr.a = 1;}
534         if (!scr.fiq) {cpsr.f = 1;}
535         if (!scr.irq) {cpsr.i = 1;}
536     } else if (cpsr.mode == MODE_MON) {
538         cpsr.t = sctlr.te;
539         cpsr.e = sctlr.ee;
540         cpsr.a = 1;
541         cpsr.f = 1;
542         cpsr.i = 1;
544         cpsr.t = sctlr.te;
545         cpsr.e = sctlr.ee;
548         cpsr.a = cpsr.a | abortDisable(tc);
549         cpsr.f = cpsr.f | fiqDisable(tc);
550         cpsr.i = 1;
552     cpsr.it1 = cpsr.it2 = 0;
553     cpsr.j = 0;
554     cpsr.pan = span ? 1 : saved_cpsr.pan;
555     tc->setMiscReg(MISCREG_CPSR, cpsr);
563     if (cpsr.mode == MODE_HYP) {
571     switch (cpsr.mode) {
603     DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
604             "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR),
608     pc.thumb(cpsr.t);
610     pc.jazelle(cpsr.j);
612     pc.aarch64(!cpsr.width);
613     pc.nextAArch64(!cpsr.width);
644     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
645     CPSR spsr = cpsr;
683     cpsr.mode = mode;
684     cpsr.daif = 0xf;
685     cpsr.il = 0;
686     cpsr.ss = 0;
687     cpsr.pan = span ? 1 : spsr.pan;
688     tc->setMiscReg(MISCREG_CPSR, cpsr);
697     DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
698             "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr,
702     pc.aarch64(!cpsr.width);
703     pc.nextAArch64(!cpsr.width);
730     CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
731     assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
732     assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
757             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
758             cpsr.mode = MODE_HYP;
759             tc->setMiscReg(MISCREG_CPSR, cpsr);
800     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
803     toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
805     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
849     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
850     OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
872     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
875     toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
877     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
943         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
944         if (cpsr.mode == MODE_HYP) {
1014     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1017     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
1077     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1085         if (cpsr.mode == MODE_HYP) {
1286     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1290     toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1293                 ( (source ==               DebugEvent) && hdcr.tde && (cpsr.mode !=  MODE_HYP)) ||
1294                 ( (source == SynchronousExternalAbort) && hcr.tge  && (cpsr.mode == MODE_USER))
1347     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1351     toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1354                 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1357                 ( (cpsr.mode == MODE_USER) && hcr.tge &&
1449     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1452             (cpsr.mode == MODE_HYP);
1488     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1491             (cpsr.mode == MODE_HYP);
1536     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1539     toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);