/gem5/src/arch/arm/ |
H A D | tlbi_op.cc | 43 #include "cpu/checker/cpu.hh" 54 CheckerCPU *checker = tc->getCheckerCpuPtr(); local 55 if (checker) { 56 getITBPtr(checker)->flushAllSecurity(secureLookup, 58 getDTBPtr(checker)->flushAllSecurity(secureLookup, 80 CheckerCPU *checker = tc->getCheckerCpuPtr(); local 81 if (checker) { 82 getITBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 83 getDTBPtr(checker)->flushAsid(asid, secureLookup, targetEL); 105 CheckerCPU *checker local 118 CheckerCPU *checker = tc->getCheckerCpuPtr(); local 133 CheckerCPU *checker = tc->getCheckerCpuPtr(); local 164 CheckerCPU *checker = tc->getCheckerCpuPtr(); local [all...] |
H A D | utility.cc | 50 #include "cpu/checker/cpu.hh" 140 CheckerCPU *checker = tc->getCheckerCpuPtr(); local 141 if (checker) {
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/gem5/tests/configs/ |
H A D | simple-atomic-dummychecker.py | 43 checker=True).create_root() variable
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H A D | o3-timing-checker.py | 43 checker=True).create_root() variable
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H A D | realview-o3-checker.py | 45 checker=True).create_root() variable
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H A D | realview64-o3-checker.py | 46 checker=True).create_root() variable
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H A D | base_config.py | 65 checker=False, mem_size=None, use_ruby=False): 73 checker -- Set to True to add checker CPUs 82 self.checker = checker 91 if self.checker:
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/gem5/tests/quick/se/00.hello/ |
H A D | test.py | 31 if root.system.cpu[0].checker != NULL: 32 root.system.cpu[0].checker.workload = root.system.cpu[0].workload
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/gem5/src/cpu/simple/ |
H A D | BaseSimpleCPU.py | 47 self.checker = DummyChecker(workload = self.workload) 48 self.checker.itb = ArmTLB(size = self.itb.size) 49 self.checker.dtb = ArmTLB(size = self.dtb.size)
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H A D | base.cc | 59 #include "cpu/checker/cpu.hh" 60 #include "cpu/checker/thread_context.hh" 110 if (p->checker) { 114 BaseCPU *temp_checker = p->checker; 115 checker = dynamic_cast<CheckerCPU *>(temp_checker); 116 checker->setSystem(p->system); 119 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 121 checker = NULL;
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H A D | base.hh | 52 #include "cpu/checker/cpu.hh" 100 CheckerCPU *checker; member in class:BaseSimpleCPU
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/gem5/src/cpu/o3/ |
H A D | O3CPU.py | 186 self.checker = O3Checker(workload=self.workload, 190 self.checker.itb = ArmTLB(size = self.itb.size) 191 self.checker.dtb = ArmTLB(size = self.dtb.size) 192 self.checker.cpu_id = self.cpu_id
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H A D | cpu.cc | 53 #include "cpu/checker/cpu.hh" 54 #include "cpu/checker/thread_context.hh" 150 if (params->checker) { 151 BaseCPU *temp_checker = params->checker; 152 checker = dynamic_cast<Checker<Impl> *>(temp_checker); 153 checker->setIcachePort(&this->fetch.getInstPort()); 154 checker->setSystem(params->system); 156 checker = NULL; 345 // If we're using a checker, then the TC should be the 347 if (params->checker) { [all...] |
H A D | dyn_inst_impl.hh | 174 if (this->cpu->checker) {
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H A D | commit_impl.hh | 56 #include "cpu/checker/cpu.hh" 761 if (cpu->checker) { 762 cpu->checker->handlePendingInt(); 1073 if (cpu->checker) { 1074 cpu->checker->verify(head_inst); 1234 // If instruction has faulted, let the checker execute it and 1236 if (cpu->checker) { 1238 cpu->checker->verify(head_inst);
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H A D | lsq_unit_impl.hh | 53 #include "cpu/checker/cpu.hh" 931 // only works so long as the checker doesn't try to 935 if (cpu->checker) { 936 cpu->checker->verify(storeWBIt->instruction()); 1044 // Tell the checker we've completed this instruction. Some stores 1045 // may get reported twice to the checker, but the checker can 1047 // Store conditionals cannot be sent to the checker yet, they have 1050 if (cpu->checker && !store_inst->isStoreConditional()) { 1051 cpu->checker [all...] |
H A D | cpu.hh | 686 /** Pointer to the checker, which can dynamically verify 690 Checker<Impl> *checker; member in class:FullO3CPU
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/gem5/configs/example/ |
H A D | memcheck.py | 275 for tester, checker, cache in zip(testers, checkers, tester_caches): 276 tester.port = checker.slave 277 checker.master = cache.cpu_side 289 for tester, checker in zip(testers, checkers): 290 tester.port = checker.slave 291 checker.master = xbar.slave
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H A D | se.py | 236 if options.checker:
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H A D | fs.py | 204 if options.checker:
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/gem5/util/ |
H A D | style.py | 97 epilog="""If no files are specified, the style checker tries to 109 help="""Apply the style checker to modified regions 115 parser.add_argument("--checker", "-c", choices=verifier_names, default=[], 128 verifiers = [ verifier_names[name] for name in args.checker ] \ 129 if args.checker else None
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 166 checker = Param.BaseCPU(NULL, "checker CPU") variable in class:BaseCPU 264 if self.checker != NULL: 265 self._cached_ports += ["checker.itb.walker.port", \ 266 "checker.dtb.walker.port"] 286 if self.checker != NULL: 287 self.checker.createThreads()
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H A D | base.cc | 60 #include "cpu/checker/cpu.hh" 243 // switched in later or in case it is a checker CPU 655 // Move over any table walker ports if they exist for checker 690 CheckerCPU *checker(tc.getCheckerCpuPtr()); 694 if (checker) { 695 checker->getITBPtr()->flushAll(); 696 checker->getDTBPtr()->flushAll();
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/gem5/src/cpu/minor/ |
H A D | cpu.cc | 74 if (params->checker) {
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/gem5/configs/common/ |
H A D | Simulation.py | 480 # Add checker cpu if selected 481 if options.checker: 522 if options.checker: 574 # attach the checker cpu if selected 575 if options.checker:
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