| /gem5/src/arch/generic/ |
| H A D | locked_mem.hh | 60 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| /gem5/src/arch/alpha/ |
| H A D | locked_mem.hh | 69 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
79 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| /gem5/src/arch/mips/ |
| H A D | locked_mem.hh | 63 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
69 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| /gem5/src/arch/arm/ |
| H A D | locked_mem.hh | 65 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
78 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
114 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
124 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
125 if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
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| /gem5/src/arch/riscv/ |
| H A D | locked_mem.hh | 74 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) argument
80 Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
82 if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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| /gem5/src/cpu/simple/ |
| H A D | atomic.hh | 145 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
150 Addr cacheBlockMask; member in class:AtomicSimpleCPU::AtomicCPUDPort
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| H A D | timing.hh | 222 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
225 Addr cacheBlockMask; member in class:TimingSimpleCPU::DcachePort
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| H A D | atomic.cc | 141 pkt, dcachePort.cacheBlockMask);
306 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
332 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
503 dcachePort.cacheBlockMask);
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| H A D | timing.cc | 307 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
622 dcachePort.cacheBlockMask);
961 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
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| /gem5/src/cpu/o3/ |
| H A D | lsq_unit_impl.hh | 148 loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
190 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
382 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
391 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
399 req->isCacheBlockHit(invalidate_addr, cacheBlockMask)
416 req->isCacheBlockHit(invalidate_addr, cacheBlockMask)) {
796 req->request(), cacheBlockMask);
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| H A D | lsq.hh | 560 virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask) = 0;
738 virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
812 virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
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| H A D | lsq_unit.hh | 502 Addr cacheBlockMask; member in class:LSQUnit
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| /gem5/src/cpu/minor/ |
| H A D | lsq.cc | 1130 request->request, cacheBlockMask);
1416 cacheBlockMask(~(cpu_.cacheLineSize() - 1))
1759 cacheBlockMask);
1781 cacheBlockMask);
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| H A D | lsq.hh | 616 Addr cacheBlockMask; member in class:Minor::LSQ
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