Searched refs:VectorMasterPort (Results 1 - 9 of 9) sorted by relevance

/gem5/src/cpu/testers/rubytest/
H A DRubyTester.py37 cpuInstDataPort = VectorMasterPort("cpu combo ports to inst & data caches")
38 cpuInstPort = VectorMasterPort("cpu ports to only inst caches")
39 cpuDataPort = VectorMasterPort("cpu ports to only data caches")
/gem5/src/dev/pci/
H A DCopyEngine.py38 dma = VectorMasterPort("Copy engine DMA port")
/gem5/src/mem/ruby/network/
H A DNetwork.py56 master = VectorMasterPort("CPU master port")
/gem5/src/gpu-compute/
H A DX86GPUTLB.py64 master = VectorMasterPort("Port on side closer to memory")
75 master = VectorMasterPort("Port on side closer to memory")
H A DGPU.py107 memory_port = VectorMasterPort("Port to the memory system")
108 translation_port = VectorMasterPort('Port to the TLB hierarchy')
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.py58 cpuPort = VectorMasterPort("the cpu ports")
/gem5/src/mem/
H A DXBar.py55 master = VectorMasterPort("Vector port for connecting slaves")
/gem5/src/mem/ruby/system/
H A DSequencer.py41 master = VectorMasterPort("CPU master port")
/gem5/src/python/m5/
H A Dparams.py2156 VectorMasterPort = VectorRequestPort variable
2193 'VectorMasterPort', 'VectorSlavePort']

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