1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ali Saidi
28
29from m5.SimObject import SimObject
30from m5.params import *
31from m5.proxy import *
32
33from m5.objects.PciDevice import PciDevice
34
35class CopyEngine(PciDevice):
36    type = 'CopyEngine'
37    cxx_header = "dev/pci/copy_engine.hh"
38    dma = VectorMasterPort("Copy engine DMA port")
39    VendorID = 0x8086
40    DeviceID = 0x1a38
41    Revision = 0xA2 # CM2 stepping (newest listed)
42    SubsystemID = 0
43    SubsystemVendorID = 0
44    Status = 0x0000
45    SubClassCode = 0x08
46    ClassCode = 0x80
47    ProgIF = 0x00
48    MaximumLatency = 0x00
49    MinimumGrant = 0xff
50    InterruptLine = 0x20
51    InterruptPin = 0x01
52    BAR0Size = '1kB'
53
54    ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
55    XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
56
57    latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
58    latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
59
60
61