15794SN/A# Copyright (c) 2008 The Regents of The University of Michigan 25794SN/A# All rights reserved. 35794SN/A# 45794SN/A# Redistribution and use in source and binary forms, with or without 55794SN/A# modification, are permitted provided that the following conditions are 65794SN/A# met: redistributions of source code must retain the above copyright 75794SN/A# notice, this list of conditions and the following disclaimer; 85794SN/A# redistributions in binary form must reproduce the above copyright 95794SN/A# notice, this list of conditions and the following disclaimer in the 105794SN/A# documentation and/or other materials provided with the distribution; 115794SN/A# neither the name of the copyright holders nor the names of its 125794SN/A# contributors may be used to endorse or promote products derived from 135794SN/A# this software without specific prior written permission. 145794SN/A# 155794SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165794SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175794SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185794SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195794SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205794SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215794SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225794SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235794SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245794SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255794SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265794SN/A# 275794SN/A# Authors: Ali Saidi 285794SN/A 295794SN/Afrom m5.SimObject import SimObject 305794SN/Afrom m5.params import * 315794SN/Afrom m5.proxy import * 3213665Sandreas.sandberg@arm.com 3313665Sandreas.sandberg@arm.comfrom m5.objects.PciDevice import PciDevice 345794SN/A 355794SN/Aclass CopyEngine(PciDevice): 365794SN/A type = 'CopyEngine' 3711261Sandreas.sandberg@arm.com cxx_header = "dev/pci/copy_engine.hh" 388841SN/A dma = VectorMasterPort("Copy engine DMA port") 395794SN/A VendorID = 0x8086 405794SN/A DeviceID = 0x1a38 415794SN/A Revision = 0xA2 # CM2 stepping (newest listed) 425794SN/A SubsystemID = 0 435794SN/A SubsystemVendorID = 0 445794SN/A Status = 0x0000 455794SN/A SubClassCode = 0x08 465794SN/A ClassCode = 0x80 475794SN/A ProgIF = 0x00 485794SN/A MaximumLatency = 0x00 495794SN/A MinimumGrant = 0xff 505794SN/A InterruptLine = 0x20 515794SN/A InterruptPin = 0x01 525794SN/A BAR0Size = '1kB' 535794SN/A 545794SN/A ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device") 555794SN/A XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported") 565794SN/A 575794SN/A latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed") 585794SN/A latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such") 595794SN/A 605794SN/A 61