17553SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 27553SN/A# All rights reserved. 37553SN/A# 47553SN/A# Redistribution and use in source and binary forms, with or without 57553SN/A# modification, are permitted provided that the following conditions are 67553SN/A# met: redistributions of source code must retain the above copyright 77553SN/A# notice, this list of conditions and the following disclaimer; 87553SN/A# redistributions in binary form must reproduce the above copyright 97553SN/A# notice, this list of conditions and the following disclaimer in the 107553SN/A# documentation and/or other materials provided with the distribution; 117553SN/A# neither the name of the copyright holders nor the names of its 127553SN/A# contributors may be used to endorse or promote products derived from 137553SN/A# this software without specific prior written permission. 147553SN/A# 157553SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167553SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177553SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187553SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197553SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207553SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217553SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227553SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237553SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247553SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257553SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267553SN/A# 277553SN/A# Authors: Brad Beckmann 287553SN/A 297553SN/Afrom m5.SimObject import SimObject 307553SN/Afrom m5.params import * 317553SN/Afrom m5.proxy import * 327553SN/A 3313892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 3413665Sandreas.sandberg@arm.com 357553SN/Aclass DirectedGenerator(SimObject): 367553SN/A type = 'DirectedGenerator' 377553SN/A abstract = True 389338SAndreas.Sandberg@arm.com cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh" 397553SN/A num_cpus = Param.Int("num of cpus") 408832SAli.Saidi@ARM.com system = Param.System(Parent.any, "System we belong to") 417553SN/A 427553SN/Aclass SeriesRequestGenerator(DirectedGenerator): 437553SN/A type = 'SeriesRequestGenerator' 449338SAndreas.Sandberg@arm.com cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh" 457553SN/A addr_increment_size = Param.Int(64, "address increment size") 469365Snilay@cs.wisc.edu num_series = Param.UInt32(1, 479365Snilay@cs.wisc.edu "number of different address streams to generate") 489365Snilay@cs.wisc.edu percent_writes = Param.Percent(50, "percent of access that are writes") 497553SN/A 507553SN/Aclass InvalidateGenerator(DirectedGenerator): 517553SN/A type = 'InvalidateGenerator' 529338SAndreas.Sandberg@arm.com cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" 537553SN/A addr_increment_size = Param.Int(64, "address increment size") 547553SN/A 5513892Sgabeblack@google.comclass RubyDirectedTester(ClockedObject): 567553SN/A type = 'RubyDirectedTester' 579338SAndreas.Sandberg@arm.com cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" 588839Sandreas.hansson@arm.com cpuPort = VectorMasterPort("the cpu ports") 597553SN/A requests_to_complete = Param.Int("checks to complete") 607553SN/A generator = Param.DirectedGenerator("the request generator") 61