/gem5/src/mem/ |
H A D | secure_port_proxy.hh | 77 bool tryMemsetBlob(Addr addr, uint8_t val, int size) const override;
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/gem5/src/arch/arm/ |
H A D | types.hh | 239 set(Addr val) argument 241 Base::set(val); 242 npc(val + (thumb() ? 2 : 4)); 245 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), argument 247 { set(val); } 256 illegalExec(bool val) argument 258 _illegalExec = val; 268 thumb(bool val) argument 270 if (val) 283 nextThumb(bool val) argument 308 jazelle(bool val) argument 323 nextJazelle(bool val) argument 338 aarch64(bool val) argument 353 nextAArch64(bool val) argument 432 instNPC(Addr val) argument 451 instIWNPC(Addr val) argument 481 instAIWNPC(Addr val) argument [all...] |
/gem5/src/arch/arm/insts/ |
H A D | vfp.cc | 221 fixDest(bool flush, bool defaultNan, fpType val, fpType op1) argument 223 int fpClass = std::fpclassify(val); 226 const bool single = (sizeof(val) == sizeof(float)); 230 val = bitsToFp(qnan, junk); 232 val = bitsToFp(fpToBits(op1) | qnan, junk); 235 // Turn val into a zero with the correct sign; 237 val = bitsToFp(fpToBits(val) & bitMask, junk); 241 return val; 245 float fixDest<float>(bool flush, bool defaultNan, float val, floa 251 fixDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument 292 fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument 327 fixFpDFpSDest(FPSCR fpscr, double val) argument 363 fixFpSFpDDest(FPSCR fpscr, float val) argument 665 vfpUFixedToFpS(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm) argument 683 vfpSFixedToFpS(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm) argument 703 vfpUFixedToFpD(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm) argument 722 vfpSFixedToFpD(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm) argument [all...] |
H A D | static_inst.hh | 203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, argument 229 if ( (!nmfi || !((val >> 6) & 0x1)) && 234 OperatingMode newMode = (OperatingMode) (val & mask(5)); 277 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 281 spsrWriteByInstr(uint32_t spsr, uint32_t val, argument 295 return ((spsr & ~bitMask) | (val & bitMask)); 305 setNextPC(ExecContext *xc, Addr val) argument 308 pc.instNPC(val); 314 cSwap(T val, bool big) argument 317 return gtobe(val); 325 cSwap(T val, bool big) argument 347 setIWNextPC(ExecContext *xc, Addr val) argument 357 setAIWNextPC(ExecContext *xc, Addr val) argument [all...] |
/gem5/src/arch/x86/insts/ |
H A D | static_inst.hh | 107 inline uint64_t merge(uint64_t into, uint64_t val, int size) const argument 112 reg.H = val; 118 reg.L = val; 121 reg.X = val; 126 reg.E = val; 129 reg.R = val;
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.cpp | 229 i->src1.val = -1; 231 i->src2.val = -1; 233 i->dst.val = -1; 249 i->src1.val = opcode&0x07; 271 i->src1.val = opcode&1; 299 i->src1.val = opcode&0x07; 321 i->src1.val = opcode&1; 358 i->src1.val = opcode&0x07; 360 i->dst.val = opcode&0x07; 379 i->src1.val [all...] |
/gem5/ext/fputils/tests/ |
H A D | fp80_cvtf.c | 61 double val = ldexp(x, exp); local 62 test_cvtf(name, val);
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | hppa.h | 123 #define QUICKTHREADS_SPUT(top, at, val) \ 124 (((qt_word_t *)(top))[-(at)] = (qt_word_t)(val))
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/gem5/site_scons/site_tools/ |
H A D | default.py | 64 for key,val in sorted(os.environ.iteritems()): 67 env['ENV'][key] = val
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/gem5/src/arch/power/ |
H A D | isa.hh | 79 setMiscRegNoEffect(int misc_reg, RegVal val) argument 85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
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H A D | process.hh | 56 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/arch/riscv/ |
H A D | isa.hh | 79 void setMiscRegNoEffect(int misc_reg, RegVal val); 80 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
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H A D | isa.cc | 169 ISA::setMiscRegNoEffect(int misc_reg, RegVal val) argument 175 DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val); 176 miscRegFile[misc_reg] = val; 180 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument 189 ->setIP(val); 192 ->setIE(val); 194 setMiscRegNoEffect(misc_reg, val);
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/gem5/src/arch/x86/bios/ |
H A D | e820.cc | 50 void writeVal(T val, PortProxy& proxy, Addr &addr) argument 52 T guestVal = htog(val);
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/gem5/src/arch/power/insts/ |
H A D | floating.hh | 71 isNan(float val) const 73 void *val_ptr = &val; 79 isNan(double val) const 81 void *val_ptr = &val;
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/gem5/src/arch/mips/ |
H A D | isa.hh | 96 RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val); 97 void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0); 98 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 101 void setMiscReg(int misc_reg, RegVal val,
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H A D | process.hh | 57 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/cpu/ |
H A D | nativetrace.hh | 91 checkReg(const char * regName, T &val, T &realVal) argument 93 if (val != realVal) 96 regName, realVal, val);
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/gem5/src/arch/x86/ |
H A D | utility.hh | 127 * @param val New rflags value to store in TC 129 void setRFlags(ThreadContext *tc, uint64_t val); 134 inline uint64_t getDoubleBits(double val) { argument 135 return *(uint64_t *)(&val);
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H A D | isa.cc | 155 ISA::setMiscRegNoEffect(int miscReg, RegVal val) argument 193 regVal[miscReg] = val & mask(reg_width); 197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) argument 199 RegVal newVal = val; 204 CR0 toggled = regVal[miscReg] ^ val; 205 CR0 newCR0 = val; 241 CR4 toggled = regVal[miscReg] ^ val; 252 SegAttr toggled = regVal[miscReg] ^ val; 253 SegAttr newCSAttr = val; 279 val, [all...] |
/gem5/src/arch/alpha/ |
H A D | isa.hh | 73 void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 80 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 81 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
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/gem5/src/dev/arm/ |
H A D | generic_timer.cc | 142 ArchTimer::setCompareValue(uint64_t val) argument 144 _counterLimit = val; 149 ArchTimer::setTimerValue(uint32_t val) argument 151 setCompareValue(value() + sext<32>(val)); 155 ArchTimer::setControl(uint32_t val) argument 157 ArchTimerCtrl new_ctl = val; 173 ArchTimer::setOffset(uint64_t val) argument 175 _offset = val; 315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) argument 322 systemCounter.setFreq(val); 511 setMiscReg(int reg, RegVal val) argument [all...] |
H A D | gic_v3_cpu_interface.cc | 734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) argument 738 miscRegName[misc_reg], val); 747 return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 750 setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val); 770 return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 792 return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 795 int int_id = val & 0xffffff; 820 int int_id = val & 0xffffff; 862 return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 865 int int_id = val 1768 generateSGI(RegVal val, Gicv3::GroupId group) argument [all...] |
H A D | generic_timer.hh | 97 void setKernelControl(uint32_t val) { _regCntkctl = val; } argument 100 void setHypControl(uint32_t val) { _regCnthctl = val; } argument 163 void setCompareValue(uint64_t val); 168 void setTimerValue(uint32_t val); 172 void setControl(uint32_t val); 175 void setOffset(uint64_t val); 226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val); 289 void setMiscReg(int misc_reg, RegVal val) overrid [all...] |
/gem5/src/cpu/o3/ |
H A D | cpu.hh | 348 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid); 353 void setMiscReg(int misc_reg, RegVal val, ThreadID tid); 398 setVecLane(PhysRegIdPtr phys_reg, const LD& val) argument 401 return regFile.setVecLane(phys_reg, val); 412 void setIntReg(PhysRegIdPtr phys_reg, RegVal val); 414 void setFloatReg(PhysRegIdPtr phys_reg, RegVal val); 416 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 418 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 420 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 422 void setCCReg(PhysRegIdPtr phys_reg, RegVal val); 446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument [all...] |