| /gem5/src/sim/ |
| H A D | insttracer.hh | 259 getInstRecord(Tick when, ThreadContext *tc,
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| /gem5/src/arch/x86/ |
| H A D | pagetable_walker.hh | 97 ThreadContext *tc; member in class:X86ISA::Walker::WalkerState
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| /gem5/src/cpu/checker/ |
| H A D | cpu.hh | 135 ThreadContext *tc; member in class:CheckerCPU
519 void mwaitAtomic(ThreadContext *tc) override
520 { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
598 ThreadContext *tcBase() override { return tc; }
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| /gem5/src/cpu/ |
| H A D | exec_context.hh | 339 virtual void mwaitAtomic(ThreadContext *tc) = 0;
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| H A D | simple_thread.hh | 221 void initMemProxies(ThreadContext *tc) override
223 ThreadState::initMemProxies(tc);
262 void copyArchRegs(ThreadContext *tc) override;
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| H A D | base_dyn_inst.hh | 956 void mwaitAtomic(ThreadContext *tc) argument
957 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
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| /gem5/src/cpu/o3/ |
| H A D | cpu.cc | 338 ThreadContext *tc; local
343 tc = o3_tc;
348 tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
357 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
360 this->thread[tid]->tc = tc;
363 this->threadContexts.push_back(tc);
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| H A D | rename_impl.hh | 1068 ThreadContext *tc = inst->tcBase(); local
1078 renamed_reg = map->lookup(tc->flattenRegId(src_reg));
1135 ThreadContext *tc = inst->tcBase(); local
1144 RegId flat_dest_regid = tc->flattenRegId(dest_reg);
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| H A D | fetch.hh | 130 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, argument
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| H A D | lsq.hh | 732 ThreadContext* tc, BaseTLB::Mode mode);
804 ThreadContext* tc, BaseTLB::Mode mode);
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| H A D | lsq_unit_impl.hh | 379 ThreadContext *tc = cpu->getContext(x); local
382 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
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| H A D | lsq_impl.hh | 774 ThreadContext* tc, BaseTLB::Mode mode)
807 ThreadContext* tc, BaseTLB::Mode mode)
773 finish(const Fault &fault, const RequestPtr &req, ThreadContext* tc, BaseTLB::Mode mode) argument
806 finish(const Fault &fault, const RequestPtr &req, ThreadContext* tc, BaseTLB::Mode mode) argument
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| /gem5/src/arch/arm/ |
| H A D | miscregs.cc | 1061 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc) argument
1063 SCR scr = tc->readMiscReg(MISCREG_SCR);
1064 return snsBankedIndex(reg, tc, scr.ns);
1068 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns) argument
1072 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1073 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1079 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc) argument
1081 SCR scr = tc->readMiscReg(MISCREG_SCR);
1082 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument
1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument
[all...] |
| H A D | pmu.cc | 97 PMU::setThreadContext(ThreadContext *tc) argument
99 DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
103 interrupt = pmu_params->interrupt->get(tc);
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| H A D | pmu.hh | 116 void setThreadContext(ThreadContext *tc) override;
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| /gem5/src/arch/mips/ |
| H A D | isa.cc | 435 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) argument
476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument
490 scheduleCP0Update(tc->getCpuPtr(), Cycles(1));
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| /gem5/src/cpu/minor/ |
| H A D | exec_context.hh | 453 void mwaitAtomic(ThreadContext *tc) override
454 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
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| H A D | fetch1.cc | 241 ThreadContext *tc, BaseTLB::Mode mode)
240 finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) argument
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| /gem5/src/cpu/simple/ |
| H A D | exec_context.hh | 561 mwaitAtomic(ThreadContext *tc) override
563 cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
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| /gem5/ext/mcpat/cacti/ |
| H A D | htree2.cc | 114 double tc = 2 * tr_R_on(nsize * min_w_nmos, NCH, 1) * local
117 delay += horowitz(w1.out_rise_time, tc,
168 double tc = res_nor * cap_nand_out + (res_nor + res_ptrans) * cap_ptrans_out; local
171 delay += horowitz(w1.out_rise_time, tc,
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| /gem5/src/dev/net/ |
| H A D | dist_iface.hh | 642 static void toggleSync(ThreadContext *tc);
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| /gem5/src/cpu/kvm/ |
| H A D | base.hh | 150 ThreadContext *tc; member in class:BaseKvmCPU
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| /gem5/src/dev/arm/ |
| H A D | gic_v3_redistributor.cc | 983 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
984 uint64_t mpidr = getMPIDR(gic->getSystem(), tc);
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| H A D | gic_v3_cpu_interface.hh | 352 void setThreadContext(ThreadContext *tc) override;
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| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.cc | 193 auto p = sender_state->tc->getProcessPtr();
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