Lines Matching refs:tc
1061 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1063 SCR scr = tc->readMiscReg(MISCREG_SCR);
1064 return snsBankedIndex(reg, tc, scr.ns);
1068 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1072 reg_as_int += (ArmSystem::haveSecurity(tc) &&
1073 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1079 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1081 SCR scr = tc->readMiscReg(MISCREG_SCR);
1082 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1121 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1126 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1131 ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1136 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1159 if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1163 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1170 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1175 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1180 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;