Searched refs:system (Results 226 - 250 of 289) sorted by relevance

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/gem5/src/dev/arm/
H A Dsmmu_v3.cc54 #include "sim/system.hh"
58 system(*params->system),
59 masterId(params->system->getMasterId(this)),
223 if (system.isAtomicMode()) {
225 } else if (system.isTimingMode()) {
372 if (system.isAtomicMode()) {
375 } else if (system.isTimingMode()) {
H A Dsmmu_v3_proc.cc43 #include "sim/system.hh"
128 if (smmu.system.isTimingMode())
H A DSMMUv3.py86 system = Param.System(Parent.any, "System this device is part of") variable in class:SMMUv3
H A Drv_ctrl.cc47 #include "sim/system.hh"
163 // A request is being submitted to read/write the system control
307 ThermalModel * tm = system->getThermalModel();
/gem5/util/
H A Dcheckpoint_aggregator.py50 os.system("mkdir -p " + output_path)
52 agg_mem_file = open(output_path + "/system.physmem.store0.pmem", "wb+")
82 elif sec == "system":
98 pages = int(config.get("system", "pagePtr"))
102 f = open(cpts[i] + "/system.physmem.store0.pmem", "rb")
117 merged_config.add_section("system")
118 merged_config.set("system", "pagePtr", page_ptr)
119 merged_config.set("system", "nextPID", len(cpts))
134 merged_config.set("system.physmem.store0", "range_size", page_ptr * 4 * 1024)
/gem5/src/dev/alpha/
H A DTsunami.py71 system = Param.System(Parent.any, "system") variable in class:Tsunami
/gem5/src/dev/sparc/
H A DT1000.py60 system = Param.System(Parent.any, "system") variable in class:T1000
/gem5/src/arch/arm/
H A Dprocess.cc59 #include "sim/system.hh"
110 ThreadContext * tc = system->getThreadContext(contextIds[i]);
129 ThreadContext * tc = system->getThreadContext(contextIds[i]);
211 ThreadContext *tc = system->getThreadContext(contextIds[0]);
285 //Bits which describe the system hardware capabilities
300 //The system page size
450 ThreadContext *tc = system->getThreadContext(contextIds[0]);
/gem5/src/gpu-compute/
H A DGPU.py100 system = Param.System(Parent.any, "system object") variable in class:ComputeUnit
107 memory_port = VectorMasterPort("Port to the memory system")
/gem5/src/arch/x86/
H A Dpagetable_walker.hh52 #include "sim/system.hh"
208 funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
H A Dfaults.cc219 dataAttr.system = 1;
241 codeAttr.system = 1;
/gem5/src/sim/
H A Dprocess.hh120 // After getting registered with system object, tell process which
121 // system-wide context id it is assigned.
168 // system object which owns this process
169 System *system; member in class:Process
171 Stats::Scalar numSyscalls; // track how many system calls are executed
205 * Redirect file path if it matches any keys initialized by system object.
216 * directory for the purpose of executing system calls which depend on
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh60 * the memory system, based on a collection of simple generator
64 * system components that are not yet modelled in detail, e.g. a video
73 * The system used to determine which mode we are currently operating
76 System *const system; member in class:BaseTrafficGen
H A Dtraffic_gen.cc54 #include "sim/system.hh"
85 if (system->isTimingMode()) {
/gem5/src/cpu/
H A DBaseCPU.py152 system = Param.System(Parent.any, "system object") variable in class:BaseCPU
321 platform, found = self.system.unproxy(self).find_any(Platform)
326 "system or multiple CPUs may not start")
/gem5/src/cpu/o3/
H A Dcpu.cc69 #include "sim/system.hh"
141 system(params->system),
154 checker->setSystem(params->system);
779 src_tc = system->threadContexts[tid];
1161 if (!system->isTimingMode()) {
1162 fatal("The O3 CPU requires the memory system to be in "
1521 system->totalNumInsts++;
1525 system->instEventQueue.serviceEvents(system
[all...]
/gem5/src/mem/cache/
H A Dbase.hh82 #include "sim/system.hh"
373 * system), effectively making this MSHR the ordering point.
913 System *system; member in class:BaseCache
1196 assert(pkt->req->masterId() < system->maxMasters());
1207 assert(pkt->req->masterId() < system->maxMasters());
/gem5/ext/pybind11/tools/
H A Dmkdoc.py243 if platform.system() == 'Darwin':
256 elif platform.system() == 'Linux':
/gem5/util/stats/
H A Doutput.py124 proxy.dict['system'] = self.info[job.system]
/gem5/ext/sst/
H A Dgem5.cc58 #include <sim/system.hh>
/gem5/src/arch/mips/
H A Dprocess.cc47 #include "sim/system.hh"
104 // Set the system page size
191 ThreadContext *tc = system->getThreadContext(contextIds[0]);
/gem5/src/arch/power/
H A Dprocess.cc47 #include "sim/system.hh"
111 //Bits which describe the system hardware capabilities
114 //The system page size
265 ThreadContext *tc = system->getThreadContext(contextIds[0]);
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc48 #include "sim/system.hh"
95 masterId(p->system->getMasterId(this))
263 // (2) mem/ruby/system/RubyPort.cc converts these to RubyRequestType_LD,
265 // (3) mem/ruby/system/Sequencer.cc sends these to the cache controllers
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.cc50 #include "sim/system.hh"
56 _masterId(p->system->getMasterId(this)),
/gem5/src/mem/
H A Dcoherent_xbar.hh69 * for the L1-to-L2 buses and as the main system interconnect. @sa
272 * Keep a pointer to the system to be allow to querying memory system
275 System *system; member in class:CoherentXBar

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