/gem5/src/dev/arm/ |
H A D | smmu_v3.cc | 54 #include "sim/system.hh" 58 system(*params->system), 59 masterId(params->system->getMasterId(this)), 223 if (system.isAtomicMode()) { 225 } else if (system.isTimingMode()) { 372 if (system.isAtomicMode()) { 375 } else if (system.isTimingMode()) {
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H A D | smmu_v3_proc.cc | 43 #include "sim/system.hh" 128 if (smmu.system.isTimingMode())
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H A D | SMMUv3.py | 86 system = Param.System(Parent.any, "System this device is part of") variable in class:SMMUv3
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H A D | rv_ctrl.cc | 47 #include "sim/system.hh" 163 // A request is being submitted to read/write the system control 307 ThermalModel * tm = system->getThermalModel();
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/gem5/util/ |
H A D | checkpoint_aggregator.py | 50 os.system("mkdir -p " + output_path) 52 agg_mem_file = open(output_path + "/system.physmem.store0.pmem", "wb+") 82 elif sec == "system": 98 pages = int(config.get("system", "pagePtr")) 102 f = open(cpts[i] + "/system.physmem.store0.pmem", "rb") 117 merged_config.add_section("system") 118 merged_config.set("system", "pagePtr", page_ptr) 119 merged_config.set("system", "nextPID", len(cpts)) 134 merged_config.set("system.physmem.store0", "range_size", page_ptr * 4 * 1024)
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/gem5/src/dev/alpha/ |
H A D | Tsunami.py | 71 system = Param.System(Parent.any, "system") variable in class:Tsunami
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/gem5/src/dev/sparc/ |
H A D | T1000.py | 60 system = Param.System(Parent.any, "system") variable in class:T1000
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/gem5/src/arch/arm/ |
H A D | process.cc | 59 #include "sim/system.hh" 110 ThreadContext * tc = system->getThreadContext(contextIds[i]); 129 ThreadContext * tc = system->getThreadContext(contextIds[i]); 211 ThreadContext *tc = system->getThreadContext(contextIds[0]); 285 //Bits which describe the system hardware capabilities 300 //The system page size 450 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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/gem5/src/gpu-compute/ |
H A D | GPU.py | 100 system = Param.System(Parent.any, "system object") variable in class:ComputeUnit 107 memory_port = VectorMasterPort("Port to the memory system")
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/gem5/src/arch/x86/ |
H A D | pagetable_walker.hh | 52 #include "sim/system.hh" 208 funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
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H A D | faults.cc | 219 dataAttr.system = 1; 241 codeAttr.system = 1;
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/gem5/src/sim/ |
H A D | process.hh | 120 // After getting registered with system object, tell process which 121 // system-wide context id it is assigned. 168 // system object which owns this process 169 System *system; member in class:Process 171 Stats::Scalar numSyscalls; // track how many system calls are executed 205 * Redirect file path if it matches any keys initialized by system object. 216 * directory for the purpose of executing system calls which depend on
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | base.hh | 60 * the memory system, based on a collection of simple generator 64 * system components that are not yet modelled in detail, e.g. a video 73 * The system used to determine which mode we are currently operating 76 System *const system; member in class:BaseTrafficGen
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H A D | traffic_gen.cc | 54 #include "sim/system.hh" 85 if (system->isTimingMode()) {
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 152 system = Param.System(Parent.any, "system object") variable in class:BaseCPU 321 platform, found = self.system.unproxy(self).find_any(Platform) 326 "system or multiple CPUs may not start")
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/gem5/src/cpu/o3/ |
H A D | cpu.cc | 69 #include "sim/system.hh" 141 system(params->system), 154 checker->setSystem(params->system); 779 src_tc = system->threadContexts[tid]; 1161 if (!system->isTimingMode()) { 1162 fatal("The O3 CPU requires the memory system to be in " 1521 system->totalNumInsts++; 1525 system->instEventQueue.serviceEvents(system [all...] |
/gem5/src/mem/cache/ |
H A D | base.hh | 82 #include "sim/system.hh" 373 * system), effectively making this MSHR the ordering point. 913 System *system; member in class:BaseCache 1196 assert(pkt->req->masterId() < system->maxMasters()); 1207 assert(pkt->req->masterId() < system->maxMasters());
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/gem5/ext/pybind11/tools/ |
H A D | mkdoc.py | 243 if platform.system() == 'Darwin': 256 elif platform.system() == 'Linux':
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/gem5/util/stats/ |
H A D | output.py | 124 proxy.dict['system'] = self.info[job.system]
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/gem5/ext/sst/ |
H A D | gem5.cc | 58 #include <sim/system.hh>
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/gem5/src/arch/mips/ |
H A D | process.cc | 47 #include "sim/system.hh" 104 // Set the system page size 191 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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/gem5/src/arch/power/ |
H A D | process.cc | 47 #include "sim/system.hh" 111 //Bits which describe the system hardware capabilities 114 //The system page size 265 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.cc | 48 #include "sim/system.hh" 95 masterId(p->system->getMasterId(this)) 263 // (2) mem/ruby/system/RubyPort.cc converts these to RubyRequestType_LD, 265 // (3) mem/ruby/system/Sequencer.cc sends these to the cache controllers
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.cc | 50 #include "sim/system.hh" 56 _masterId(p->system->getMasterId(this)),
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/gem5/src/mem/ |
H A D | coherent_xbar.hh | 69 * for the L1-to-L2 buses and as the main system interconnect. @sa 272 * Keep a pointer to the system to be allow to querying memory system 275 System *system; member in class:CoherentXBar
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