Searched refs:port (Results 26 - 50 of 196) sorted by relevance

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/gem5/tests/configs/
H A Dtgen-simple-mem.py65 system.cpu.port = system.monitor.slave
68 # connect the system port even if it is not used in this example
72 system.physmem.port = system.membus.master
H A Dtgen-dram-ctrl.py62 system.cpu.port = system.monitor.slave
65 # connect the system port even if it is not used in this example
69 system.physmem.port = system.membus.master
H A Do3-timing-ruby.py47 system.physmem.port = system.membus.master
52 # Connect the system port for loading of binaries etc
/gem5/src/sim/
H A Ddebug.cc134 // Set remote GDB base port. 0 means disable remote GDB.
137 setRemoteGDBPort(int port) argument
139 remote_gdb_base_port = port;
H A Dport.hh72 * to InvalidPortID in case this port is not part of a vector.
77 * A pointer to this port's peer.
83 * Whether this port is currently connected to a peer port.
91 * @param _id A port identifier for vector ports
102 /** Return a reference to this port's peer. */
105 /** Return port name (for DPRINTF). */
108 /** Get the port id. */
111 /** Attach to a peer port. */
119 /** Dettach from a peer port
151 operator <<(std::ostream &os, const Port &port) argument
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/gem5/util/tlm/src/
H A Dsim_control.hh117 void registerSlavePort(const std::string& name, SCSlavePort* port);
118 void registerMasterPort(const std::string& name, SCMasterPort* port);
/gem5/util/tlm/conf/
H A Dtlm_master.py61 # Create a external TLM port:
68 system.physmem.port = system.membus.master
69 system.tlm.port = system.membus.slave
H A Dtlm_slave.py37 # external TLM port for SystemC co-simulation
63 # Create a external TLM port:
70 system.cpu.port = system.membus.slave
72 system.membus.master = system.tlm.port
/gem5/src/arch/x86/
H A DX86TLB.py48 port = MasterPort("Port for the hardware table walker") variable in class:X86PagetableWalker
H A Dx86_traits.hh81 x86IOAddress(const uint32_t port) argument
83 return PhysAddrPrefixIO | port;
/gem5/src/mem/
H A Dfs_translating_port_proxy.hh53 * simulated system. Via the port proxies all the accesses go through
54 * an actual port and thus are transparent to a potentially
69 * port. If a thread context is provided the address can alway be
84 FSTranslatingPortProxy(MasterPort &port,
H A Dsimple_mem.cc53 port(name() + ".port", *this), latency(p->latency),
68 if (port.isConnected()) {
69 port.sendRangeChange();
200 port.sendRetryReq();
210 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
247 if (if_name != "port") {
250 return port;
/gem5/src/systemc/ext/tlm_core/1/req_rsp/ports/
H A Devent_finder.hh60 dynamic_cast<const IF *>(port()->_gem5Interface(0));
63 out << "port is not bound: port '" << port()->name() <<
64 "' (" << port()->kind() << ")";
/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py64 port = MasterPort("Master port") variable in class:BaseTrafficGen
119 self.port = bus.slave
126 self.port = dc.cpu_side
/gem5/src/python/m5/util/
H A Ddot_writer.py96 # create nodes per port
98 port = simNode._port_refs.get(port_name, None)
99 if port != None:
113 port = simNode._port_refs.get(port_name, None)
114 if port != None:
119 if isinstance(port, PortRef):
120 if port.peer:
121 dot_add_edge(simNode, callgraph, full_port_name, port)
123 for p in port.elements:
131 def dot_add_edge(simNode, callgraph, full_port_name, port)
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/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_module.cpp114 // Struct for temporarily storing a pointer to an interface or port.
120 port( 0 )
125 port( 0 )
130 port( &port_ )
289 sc_module::async_reset_signal_is( const sc_in<bool>& port, bool level ) argument
291 sc_reset::reset_signal_is(true, port, level);
295 sc_module::async_reset_signal_is( const sc_inout<bool>& port, bool level ) argument
297 sc_reset::reset_signal_is(true, port, level);
301 sc_module::async_reset_signal_is( const sc_out<bool>& port, bool level ) argument
303 sc_reset::reset_signal_is(true, port, leve
341 reset_signal_is( const sc_in<bool>& port, bool level ) argument
347 reset_signal_is( const sc_inout<bool>& port, bool level ) argument
353 reset_signal_is( const sc_out<bool>& port, bool level ) argument
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H A Dsc_reset.cpp70 // sc_reset_finder - place holder class for a port reset signal until it is
71 // bound and an interface class is available. When the port
236 // process with the sc_reset object instance associated with the supplied port.
237 // If the port does not yet have a pointer to its sc_signal<bool> instance it
239 // to set the process' reset information when the port has been bound.
243 // port = port for sc_signal<bool> that will provide the reset signal.
246 void sc_reset::reset_signal_is( bool async, const sc_in<bool>& port, bool level) argument
259 iface_p = DCAST<const sc_signal_in_if<bool>*>(port.get_interface());
263 new sc_reset_finder( async, &port, leve
271 reset_signal_is( bool async, const sc_inout<bool>& port, bool level ) argument
297 reset_signal_is( bool async, const sc_out<bool>& port, bool level ) argument
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/gem5/src/systemc/tests/systemc/communication/ports/test01/
H A Dtest01.cpp51 sc_port<sc_signal_in_if<float> > port; local
74 port( "port" ),
100 WRITE( a.port );
/gem5/src/systemc/
H A Dsc_port_wrapper.hh37 #include "sim/port.hh"
64 port() function in class:sc_gem5::ScPortWrapper
80 port_.bind(beer->port());
85 fatal("Attempt to bind sc_port %s to incompatible port %s.",
121 "Attempt to bind sc_interface %s to incompatible port %s.",
145 port() function in class:sc_gem5::ScExportWrapper
161 "Attempt to bind sc_export %s to incompatible port %s.",
/gem5/src/systemc/core/
H A Dmodule.cc118 auto port = *portIt; local
120 port->vbind(*proxy->interface());
122 port->vbind(*proxy->port());
/gem5/src/dev/virtio/
H A DVirtIO9P.py71 port = Param.String("564", "9P server port") variable in class:VirtIO9PSocket
/gem5/src/cpu/testers/memtest/
H A DMemTest.py69 port = MasterPort("Port to the memory system") variable in class:MemTest
/gem5/src/systemc/tests/systemc/1666-2011-compliance/sc_vector/
H A Dsc_vector.cpp112 sc_port<i_f> port; member in struct:Initiator1
115 : port("port")
123 port->method();
151 sc_vector<Sub> kids; // Vector-of-modules, each with a port p
223 sc_assemble_vector(initiator_vec, &Initiator1::port).bind( sc_assemble_vector(target_vec, &Target::xp) );
226 sc_vector_assembly< Initiator1, sc_port<i_f> > assembly = sc_assemble_vector(initiator_vec, &Initiator1::port);
228 sc_assert( &*(assembly.begin()) == &(*initiator_vec.begin()).port );
229 // sc_assert( &*(assembly.end()) == &(*initiator_vec.end()).port );
233 sc_assert( &assembly[i] == &initiator_vec[i].port );
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/gem5/src/cpu/minor/
H A Dlsq.cc62 port(port_),
80 SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
82 ExecContext context(port.cpu, thread, port.execute, inst);
88 DPRINTFS(MinorMem, (&port),
99 DPRINTFS(MinorMem, (&port), "Complete disabled mem access for inst:%s\n",
102 SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
105 ExecContext context(port.cpu, thread, port.execute, inst);
116 port
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/gem5/ext/systemc/src/sysc/communication/
H A Dsc_event_finder.h50 const sc_port_base& port() const function in class:sc_core::sc_event_finder
68 const sc_port_base& m_port; // port providing the event.
126 DCAST<const IF*>( port().get_interface() );
128 report_error( SC_ID_FIND_EVENT_, "port is not bound" );
149 // finder for each port for each type of event, e.g., pos(), neg(), and
150 // value_change(). The event finder persists as long as the port does,
152 // allocated for each event type per port there is not a potential
157 // the dynamically allocated instances can be freed after port binding

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