1# Copyright (c) 2012-2013,2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Uri Wiener 38# Sascha Bischoff 39 40##################################################################### 41# 42# System visualization using DOT 43# 44# While config.ini and config.json provide an almost complete listing 45# of a system's components and connectivity, they lack a birds-eye 46# view. The output generated by do_dot() is a DOT-based figure (as a 47# pdf and an editable svg file) and its source dot code. Nodes are 48# components, and edges represent the memory hierarchy: the edges are 49# directed, from a master to slave. Initially all nodes are 50# generated, and then all edges are added. do_dot should be called 51# with the top-most SimObject (namely root but not necessarily), the 52# output folder and the output dot source filename. From the given 53# node, both processes (node and edge creation) is performed 54# recursivly, traversing all children of the given root. 55# 56# pydot is required. When missing, no output will be generated. 57# 58##################################################################### 59 60from __future__ import print_function 61from __future__ import absolute_import 62 63import m5, os, re 64from m5.SimObject import isRoot, isSimObjectVector 65from m5.params import PortRef, isNullPointer 66from m5.util import warn 67try: 68 import pydot 69except: 70 pydot = False 71 72def simnode_children(simNode): 73 for child in simNode._children.values(): 74 if isNullPointer(child): 75 continue 76 if isSimObjectVector(child): 77 for obj in child: 78 if not isNullPointer(obj): 79 yield obj 80 else: 81 yield child 82 83# need to create all nodes (components) before creating edges (memory channels) 84def dot_create_nodes(simNode, callgraph): 85 if isRoot(simNode): 86 label = "root" 87 else: 88 label = simNode._name 89 full_path = re.sub('\.', '_', simNode.path()) 90 # add class name under the label 91 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 92 93 # each component is a sub-graph (cluster) 94 cluster = dot_create_cluster(simNode, full_path, label) 95 96 # create nodes per port 97 for port_name in simNode._ports.keys(): 98 port = simNode._port_refs.get(port_name, None) 99 if port != None: 100 full_port_name = full_path + "_" + port_name 101 port_node = dot_create_node(simNode, full_port_name, port_name) 102 cluster.add_node(port_node) 103 104 # recurse to children 105 for child in simnode_children(simNode): 106 dot_create_nodes(child, cluster) 107 108 callgraph.add_subgraph(cluster) 109 110# create all edges according to memory hierarchy 111def dot_create_edges(simNode, callgraph): 112 for port_name in simNode._ports.keys(): 113 port = simNode._port_refs.get(port_name, None) 114 if port != None: 115 full_path = re.sub('\.', '_', simNode.path()) 116 full_port_name = full_path + "_" + port_name 117 port_node = dot_create_node(simNode, full_port_name, port_name) 118 # create edges 119 if isinstance(port, PortRef): 120 if port.peer: 121 dot_add_edge(simNode, callgraph, full_port_name, port) 122 else: 123 for p in port.elements: 124 if p.peer: 125 dot_add_edge(simNode, callgraph, full_port_name, p) 126 127 # recurse to children 128 for child in simnode_children(simNode): 129 dot_create_edges(child, callgraph) 130 131def dot_add_edge(simNode, callgraph, full_port_name, port): 132 peer = port.peer 133 full_peer_path = re.sub('\.', '_', peer.simobj.path()) 134 full_peer_port_name = full_peer_path + "_" + peer.name 135 136 # Each edge is encountered twice, once for each peer. We only want one 137 # edge, so we'll arbitrarily chose which peer "wins" based on their names. 138 if full_peer_port_name < full_port_name: 139 dir_type = { 140 (False, False) : 'both', 141 (True, False) : 'forward', 142 (False, True) : 'back', 143 (True, True) : 'none' 144 }[ (port.is_source, 145 peer.is_source) ] 146 edge = pydot.Edge(full_port_name, full_peer_port_name, dir=dir_type) 147 callgraph.add_edge(edge) 148 149def dot_create_cluster(simNode, full_path, label): 150 # get the parameter values of the node and use them as a tooltip 151 ini_strings = [] 152 for param in sorted(simNode._params.keys()): 153 value = simNode._values.get(param) 154 if value != None: 155 # parameter name = value in HTML friendly format 156 ini_strings.append(str(param) + "=" + 157 simNode._values[param].ini_str()) 158 # join all the parameters with an HTML newline 159 tooltip = " \\".join(ini_strings) 160 161 return pydot.Cluster( \ 162 full_path, \ 163 shape = "Mrecord", \ 164 label = label, \ 165 tooltip = "\"" + tooltip + "\"", \ 166 style = "\"rounded, filled\"", \ 167 color = "#000000", \ 168 fillcolor = dot_gen_colour(simNode), \ 169 fontname = "Arial", \ 170 fontsize = "14", \ 171 fontcolor = "#000000" \ 172 ) 173 174def dot_create_node(simNode, full_path, label): 175 return pydot.Node( \ 176 full_path, \ 177 shape = "Mrecord", \ 178 label = label, \ 179 style = "\"rounded, filled\"", \ 180 color = "#000000", \ 181 fillcolor = dot_gen_colour(simNode, True), \ 182 fontname = "Arial", \ 183 fontsize = "14", \ 184 fontcolor = "#000000" \ 185 ) 186 187# an enumerator for different kinds of node types, at the moment we 188# discern the majority of node types, with the caches being the 189# notable exception 190class NodeType: 191 SYS = 0 192 CPU = 1 193 XBAR = 2 194 MEM = 3 195 DEV = 4 196 OTHER = 5 197 198# based on the sim object, determine the node type 199def get_node_type(simNode): 200 if isinstance(simNode, m5.objects.System): 201 return NodeType.SYS 202 # NULL ISA has no BaseCPU or PioDevice, so check if these names 203 # exists before using them 204 elif 'BaseCPU' in dir(m5.objects) and \ 205 isinstance(simNode, m5.objects.BaseCPU): 206 return NodeType.CPU 207 elif 'PioDevice' in dir(m5.objects) and \ 208 isinstance(simNode, m5.objects.PioDevice): 209 return NodeType.DEV 210 elif isinstance(simNode, m5.objects.BaseXBar): 211 return NodeType.XBAR 212 elif isinstance(simNode, m5.objects.AbstractMemory): 213 return NodeType.MEM 214 else: 215 return NodeType.OTHER 216 217# based on the node type, determine the colour as an RGB tuple, the 218# palette is rather arbitrary at this point (some coherent natural 219# tones), and someone that feels artistic should probably have a look 220def get_type_colour(nodeType): 221 if nodeType == NodeType.SYS: 222 return (228, 231, 235) 223 elif nodeType == NodeType.CPU: 224 return (187, 198, 217) 225 elif nodeType == NodeType.XBAR: 226 return (111, 121, 140) 227 elif nodeType == NodeType.MEM: 228 return (94, 89, 88) 229 elif nodeType == NodeType.DEV: 230 return (199, 167, 147) 231 elif nodeType == NodeType.OTHER: 232 # use a relatively gray shade 233 return (186, 182, 174) 234 235# generate colour for a node, either corresponding to a sim object or a 236# port 237def dot_gen_colour(simNode, isPort = False): 238 # determine the type of the current node, and also its parent, if 239 # the node is not the same type as the parent then we use the base 240 # colour for its type 241 node_type = get_node_type(simNode) 242 if simNode._parent: 243 parent_type = get_node_type(simNode._parent) 244 else: 245 parent_type = NodeType.OTHER 246 247 # if this node is the same type as the parent, then scale the 248 # colour based on the depth such that the deeper levels in the 249 # hierarchy get darker colours 250 if node_type == parent_type: 251 # start out with a depth of zero 252 depth = 0 253 parent = simNode._parent 254 # find the closes parent that is not the same type 255 while parent and get_node_type(parent) == parent_type: 256 depth = depth + 1 257 parent = parent._parent 258 node_colour = get_type_colour(parent_type) 259 # slightly arbitrary, but assume that the depth is less than 260 # five levels 261 r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour) 262 else: 263 node_colour = get_type_colour(node_type) 264 r, g, b = node_colour 265 266 # if we are colouring a port, then make it a slightly darker shade 267 # than the node that encapsulates it, once again use a magic constant 268 if isPort: 269 r, g, b = map(lambda x: 0.8 * x, (r, g, b)) 270 271 return dot_rgb_to_html(r, g, b) 272 273def dot_rgb_to_html(r, g, b): 274 return "#%.2x%.2x%.2x" % (r, g, b) 275 276# We need to create all of the clock domains. We abuse the alpha channel to get 277# the correct domain colouring. 278def dot_add_clk_domain(c_dom, v_dom): 279 label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\"" 280 label = re.sub('\.', '_', str(label)) 281 full_path = re.sub('\.', '_', str(c_dom)) 282 return pydot.Cluster( \ 283 full_path, \ 284 shape = "Mrecord", \ 285 label = label, \ 286 style = "\"rounded, filled, dashed\"", \ 287 color = "#000000", \ 288 fillcolor = "#AFC8AF8F", \ 289 fontname = "Arial", \ 290 fontsize = "14", \ 291 fontcolor = "#000000" \ 292 ) 293 294def dot_create_dvfs_nodes(simNode, callgraph, domain=None): 295 if isRoot(simNode): 296 label = "root" 297 else: 298 label = simNode._name 299 full_path = re.sub('\.', '_', simNode.path()) 300 # add class name under the label 301 label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\"" 302 303 # each component is a sub-graph (cluster) 304 cluster = dot_create_cluster(simNode, full_path, label) 305 306 # create nodes per port 307 for port_name in simNode._ports.keys(): 308 port = simNode._port_refs.get(port_name, None) 309 if port != None: 310 full_port_name = full_path + "_" + port_name 311 port_node = dot_create_node(simNode, full_port_name, port_name) 312 cluster.add_node(port_node) 313 314 # Dictionary of DVFS domains 315 dvfs_domains = {} 316 317 # recurse to children 318 for child in simnode_children(simNode): 319 try: 320 c_dom = child.__getattr__('clk_domain') 321 v_dom = c_dom.__getattr__('voltage_domain') 322 except AttributeError: 323 # Just re-use the domain from above 324 c_dom = domain 325 v_dom = c_dom.__getattr__('voltage_domain') 326 pass 327 328 if c_dom == domain or c_dom == None: 329 dot_create_dvfs_nodes(child, cluster, domain) 330 else: 331 if c_dom not in dvfs_domains: 332 dvfs_cluster = dot_add_clk_domain(c_dom, v_dom) 333 dvfs_domains[c_dom] = dvfs_cluster 334 else: 335 dvfs_cluster = dvfs_domains[c_dom] 336 dot_create_dvfs_nodes(child, dvfs_cluster, c_dom) 337 338 for key in dvfs_domains: 339 cluster.add_subgraph(dvfs_domains[key]) 340 341 callgraph.add_subgraph(cluster) 342 343def do_dot(root, outdir, dotFilename): 344 if not pydot: 345 return 346 # * use ranksep > 1.0 for for vertical separation between nodes 347 # especially useful if you need to annotate edges using e.g. visio 348 # which accepts svg format 349 # * no need for hoizontal separation as nothing moves horizonally 350 callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 351 dot_create_nodes(root, callgraph) 352 dot_create_edges(root, callgraph) 353 dot_filename = os.path.join(outdir, dotFilename) 354 callgraph.write(dot_filename) 355 try: 356 # dot crashes if the figure is extremely wide. 357 # So avoid terminating simulation unnecessarily 358 callgraph.write_svg(dot_filename + ".svg") 359 callgraph.write_pdf(dot_filename + ".pdf") 360 except: 361 warn("failed to generate dot output from %s", dot_filename) 362 363def do_dvfs_dot(root, outdir, dotFilename): 364 if not pydot: 365 return 366 367 # There is a chance that we are unable to resolve the clock or 368 # voltage domains. If so, we fail silently. 369 try: 370 dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3') 371 dot_create_dvfs_nodes(root, dvfsgraph) 372 dot_create_edges(root, dvfsgraph) 373 dot_filename = os.path.join(outdir, dotFilename) 374 dvfsgraph.write(dot_filename) 375 except: 376 warn("Failed to generate dot graph for DVFS domains") 377 return 378 379 try: 380 # dot crashes if the figure is extremely wide. 381 # So avoid terminating simulation unnecessarily 382 dvfsgraph.write_svg(dot_filename + ".svg") 383 dvfsgraph.write_pdf(dot_filename + ".pdf") 384 except: 385 warn("failed to generate dot output from %s", dot_filename) 386