Searched refs:mode (Results 101 - 125 of 141) sorted by relevance

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/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.cc206 opModeToStr(mode), /* Exception level */
/gem5/src/mem/cache/
H A Dbase.hh348 * written. The write mode also affects the behaviour on filling
544 * Handle a request in atomic mode that missed in this cache
547 * handles the response. As we are in atomic mode all operations
600 * Send writebacks down the memory hierarchy in atomic mode
634 * in atomic mode, must happen after the call to recvAtomic has
720 * is called by both atomic and timing-mode accesses, and in atomic
721 * mode we don't mess with the write buffer (we just perform the
1268 * 1) When byteCount has surpassed the coallesceLimit the mode
1289 * Should writes be coalesced? This is true if the mode is set to
1295 return mode !
1366 WriteMode mode; member in class:WriteAllocator
[all...]
/gem5/src/gpu-compute/
H A Dshader.cc384 Shader::functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode) argument
386 // update senderState. Need to know the gpuTc and the TLB mode
388 new TheISA::GpuTLB::TranslationState(mode, gpuTc, false);
H A Dwavefront.hh181 uint32_t remap(uint32_t vgprIndex, uint32_t size, uint8_t mode=0);
H A Dcl_driver.cc96 ClDriver::open(ThreadContext *tc, int mode, int flags) argument
/gem5/src/arch/x86/
H A Disa.cc50 m5reg.mode = LongMode;
56 m5reg.mode = LegacyMode;
209 //Turning on long mode
213 //Turning off long mode
294 // These segments ignore their bases in 64 bit mode.
303 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
H A Ddecoder.cc182 // REX prefixes are only recognized in 64 bit mode.
183 if (prefix == RexPrefix && emi.mode.submode != SixtyFourBitMode)
277 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
318 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
543 //There is no SIB in 16 bit mode.
545 // && in 32/64 bit mode)
/gem5/src/arch/alpha/
H A Dev5.cc304 stats->mode(Kernel::user, tc);
307 stats->mode(Kernel::kernel, tc);
312 // only write two mode bits - processor mode
317 // only write two mode bits - processor mode
H A Dkernel_stats.cc86 .desc("number of protection mode switches")
102 .desc("fraction of useful protection mode switches")
114 .desc("number of ticks spent at the given mode")
172 DPRINTF(Context, "old mode=%s new mode=%s pid=%d\n",
184 Statistics::mode(cpu_mode newmode, ThreadContext *tc) function in class:AlphaISA::Kernel::Statistics
/gem5/src/arch/arm/
H A Dtable_walker.cc140 mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
202 // For atomic mode, a new WalkerState instance should be only created
203 // once per TLB. For timing mode, a new instance is generated for every
210 // If we are mixing functional mode with timing (or even
253 currState->mode = _mode;
303 currState->isFetch = (currState->mode == TLB::Execute);
304 currState->isWrite = (currState->mode == TLB::Write);
398 curr_state_copy->tc, curr_state_copy->mode);
423 currState->req, currState->tc, currState->mode);
428 currState->transState, currState->mode);
[all...]
H A Dtable_walker.hh668 /** User/privileged mode protection flag for subsequent levels of
776 /** If the mode is timing or atomic */
779 /** If the atomic mode should be functional */
782 /** Save mode for use in delayed response */
783 BaseTLB::Mode mode; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
795 /** Whether the response is delayed in timing mode due to additional
908 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
/gem5/src/arch/sparc/
H A Dtlb.cc837 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) argument
839 if (mode == Execute)
842 return translateData(req, tc, mode == Write);
847 Translation *translation, Mode mode)
850 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local
855 ThreadContext *tc, Mode mode) const
846 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
/gem5/ext/googletest/googletest/include/gtest/internal/
H A Dgtest-port.h104 // is building in C++11/C++98 mode.
325 // probably other compilers set that too in C++11 mode.
327 // Compiling in at least C++11 mode.
336 // C++11 mode when targeting Mac OS X 10.6, which has an old libstdc++
627 // feature depending on tuple with be disabled in this mode).
651 // support TR1 tuple. libc++ only provides std::tuple, in C++11 mode,
659 // in C++11 mode and libstdc++ isn't very old (binaries targeting OS X 10.6
1283 // GTEST_CHECK_ is an all-mode assert. It aborts the program if the condition
1294 // whether it is built in the debug mode or not.
1303 // An all-mode asser
2367 FOpen(const char* path, const char* mode) argument
2371 FReopen(const char* path, const char* mode, FILE* stream) argument
2374 FDOpen(int fd, const char* mode) argument
[all...]
/gem5/ext/mcpat/
H A DxmlParser.cc192 return _CXML("Error: Character code above 255 is forbidden in MultiByte char mode.");
287 static inline FILE *xfopen(XMLCSTR filename, XMLCSTR mode) { argument
288 return _wfopen(filename, mode);
335 static inline FILE *xfopen(XMLCSTR filename, XMLCSTR mode) { argument
336 return fopen(filename, mode);
426 static inline FILE *xfopen(XMLCSTR filename, XMLCSTR mode) { argument
429 if (mode[0] == _CXML('r')) f = fopen(filenameAscii, "rb");
435 static inline FILE *xfopen(XMLCSTR filename, XMLCSTR mode) { argument
436 return fopen(filename, mode);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh206 bool privileged = (cpsr.mode != MODE_USER);
233 // Now check the new mode is allowed
235 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
240 // mode ('10110'), and FIQ mode ('10001') if the Security
246 // There is no Hyp mode ('11010') in Secure state, so that
250 // Cannot move into Hyp mode directly from a Non-secure
251 // PL1 mode
254 // Cannot move out of Hyp mode with this function except
258 // Must not change to 64 bit when running in 32 bit mode
[all...]
/gem5/util/style/
H A Dverifiers.py149 def open(self, filename, mode):
151 f = file(filename, mode)
/gem5/src/sim/
H A Dsystem.cc232 System::setMemoryMode(Enums::MemoryMode mode) argument
235 memoryMode = mode;
H A Dsyscall_emul.cc561 mode_t mode = p->getSyscallArg(tc, index); local
563 auto result = mkdir(path.c_str(), mode);
1032 // fake_syscall mode, so there's no way for a process to know it's
1130 int mode = p->getSyscallArg(tc, index); local
1139 int result = fallocate(sim_fd, mode, offset, len);
1160 mode_t mode = p->getSyscallArg(tc, index); local
1162 int result = access(path.c_str(), mode);
1182 mode_t mode = p->getSyscallArg(tc, index); local
1185 auto result = mknod(path.c_str(), mode, dev);
H A Dsystem.hh137 * Is the system in atomic mode?
143 * Port::recvAtomic() when accessing memory in this mode.
151 * Is the system in timing mode?
154 * Port::recvTiming() when accessing memory in this mode.
173 * Get the memory mode of the system.
182 * Change the memory mode of the system.
186 * @param mode Mode to change to (atomic/timing/...)
188 void setMemoryMode(Enums::MemoryMode mode);
632 // Used by syscall-emulation mode. This member contains paths which need
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dillegal.S24 # Skip the rest of the test if S-mode is not present.
50 # Enter supervisor mode.
/gem5/src/cpu/o3/
H A Dthread_context_impl.hh187 // Set vector renaming mode before copying registers
188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
H A Dlsq.hh732 ThreadContext* tc, BaseTLB::Mode mode);
804 ThreadContext* tc, BaseTLB::Mode mode);
1069 /** The LSQ policy for SMT mode. */
/gem5/src/cpu/simple/
H A Dtiming.hh128 BaseTLB::Mode mode)
127 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_simcontext.cpp1846 // This function sets the mode of operation when sc_stop() is called.
1847 // mode = SC_STOP_IMMEDIATE or SC_STOP_FINISH_DELTA.
1849 void sc_set_stop_mode(sc_stop_mode mode) argument
1857 switch( mode )
1861 stop_mode = mode;
2037 Description of Modification: - sc_stop mode
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc954 // EOI mode is not set, so don't deactivate
2340 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2345 switch (cpsr.mode) {
2392 return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2400 bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
2404 } else if (!is_64 && (cpsr.mode == MODE_MON)) {

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