112771Sqtt2@cornell.edu# See LICENSE for license details. 212771Sqtt2@cornell.edu 312771Sqtt2@cornell.edu#***************************************************************************** 412771Sqtt2@cornell.edu# illegal.S 512771Sqtt2@cornell.edu#----------------------------------------------------------------------------- 612771Sqtt2@cornell.edu# 712771Sqtt2@cornell.edu# Test illegal instruction trap. 812771Sqtt2@cornell.edu# 912771Sqtt2@cornell.edu 1012771Sqtt2@cornell.edu#include "riscv_test.h" 1112771Sqtt2@cornell.edu#include "test_macros.h" 1212771Sqtt2@cornell.edu 1312771Sqtt2@cornell.eduRVTEST_RV64M 1412771Sqtt2@cornell.eduRVTEST_CODE_BEGIN 1512771Sqtt2@cornell.edu 1612771Sqtt2@cornell.edu .align 2 1712771Sqtt2@cornell.edu .option norvc 1812771Sqtt2@cornell.edu 1912771Sqtt2@cornell.edu li TESTNUM, 2 2012771Sqtt2@cornell.edubad2: 2112771Sqtt2@cornell.edu .word 0 2212771Sqtt2@cornell.edu j fail 2312771Sqtt2@cornell.edu 2412771Sqtt2@cornell.edu # Skip the rest of the test if S-mode is not present. 2512771Sqtt2@cornell.edu li t0, MSTATUS_MPP 2612771Sqtt2@cornell.edu csrc mstatus, t0 2712771Sqtt2@cornell.edu li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S 2812771Sqtt2@cornell.edu csrs mstatus, t1 2912771Sqtt2@cornell.edu csrr t2, mstatus 3012771Sqtt2@cornell.edu and t2, t2, t0 3112771Sqtt2@cornell.edu bne t1, t2, pass 3212771Sqtt2@cornell.edu 3312771Sqtt2@cornell.edu # Test vectored interrupts if they are supported. 3412771Sqtt2@cornell.edutest_vectored_interrupts: 3512771Sqtt2@cornell.edu csrwi mip, MIP_SSIP 3612771Sqtt2@cornell.edu csrwi mie, MIP_SSIP 3712771Sqtt2@cornell.edu la t0, mtvec_handler + 1 3812771Sqtt2@cornell.edu csrrw s0, mtvec, t0 3912771Sqtt2@cornell.edu csrr t0, mtvec 4012771Sqtt2@cornell.edu andi t0, t0, 1 4112771Sqtt2@cornell.edu beqz t0, msip 4212771Sqtt2@cornell.edu csrsi mstatus, MSTATUS_MIE 4312771Sqtt2@cornell.edu1: 4412771Sqtt2@cornell.edu j 1b 4512771Sqtt2@cornell.edumsip: 4612771Sqtt2@cornell.edu csrw mtvec, s0 4712771Sqtt2@cornell.edu 4812771Sqtt2@cornell.edu # Delegate supervisor software interrupts so WFI won't stall. 4912771Sqtt2@cornell.edu csrwi mideleg, MIP_SSIP 5012771Sqtt2@cornell.edu # Enter supervisor mode. 5112771Sqtt2@cornell.edu la t0, 1f 5212771Sqtt2@cornell.edu csrw mepc, t0 5312771Sqtt2@cornell.edu li t0, MSTATUS_MPP 5412771Sqtt2@cornell.edu csrc mstatus, t0 5512771Sqtt2@cornell.edu li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S 5612771Sqtt2@cornell.edu csrs mstatus, t1 5712771Sqtt2@cornell.edu mret 5812771Sqtt2@cornell.edu 5912771Sqtt2@cornell.edu1: 6012771Sqtt2@cornell.edu # Make sure WFI doesn't trap when TW=0. 6112771Sqtt2@cornell.edu wfi 6212771Sqtt2@cornell.edubad3: 6312771Sqtt2@cornell.edu .word 0 6412771Sqtt2@cornell.edu j fail 6512771Sqtt2@cornell.edu 6612771Sqtt2@cornell.edubad4: 6712771Sqtt2@cornell.edu # Make sure WFI does trap when TW=1. 6812771Sqtt2@cornell.edu wfi 6912771Sqtt2@cornell.edu j fail 7012771Sqtt2@cornell.edu 7112771Sqtt2@cornell.edu # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. 7212771Sqtt2@cornell.edu sfence.vma 7312771Sqtt2@cornell.edu csrr t0, sptbr 7412771Sqtt2@cornell.edubad5: 7512771Sqtt2@cornell.edu .word 0 7612771Sqtt2@cornell.edu j fail 7712771Sqtt2@cornell.edu 7812771Sqtt2@cornell.edubad6: 7912771Sqtt2@cornell.edu # Make sure SFENCE.VMA and sptbr do trap when TVM=1. 8012771Sqtt2@cornell.edu sfence.vma 8112771Sqtt2@cornell.edu j fail 8212771Sqtt2@cornell.edubad7: 8312771Sqtt2@cornell.edu csrr t0, sptbr 8412771Sqtt2@cornell.edu j fail 8512771Sqtt2@cornell.edu 8612771Sqtt2@cornell.edu # Make sure SRET doesn't trap when TSR=0. 8712771Sqtt2@cornell.edu la t0, bad8 8812771Sqtt2@cornell.edu csrw sepc, t0 8912771Sqtt2@cornell.edu li t0, SSTATUS_SPP 9012771Sqtt2@cornell.edu csrs sstatus, t0 9112771Sqtt2@cornell.edu li t0, SSTATUS_SPIE 9212771Sqtt2@cornell.edu csrc sstatus, t0 9312771Sqtt2@cornell.edu sret 9412771Sqtt2@cornell.edubad8: 9512771Sqtt2@cornell.edu .word 0 9612771Sqtt2@cornell.edu j fail 9712771Sqtt2@cornell.edu 9812771Sqtt2@cornell.edu # Make sure SRET does trap when TSR=1. 9912771Sqtt2@cornell.edu la t0, 1f 10012771Sqtt2@cornell.edu csrw sepc, t0 10112771Sqtt2@cornell.edubad9: 10212771Sqtt2@cornell.edu sret 10312771Sqtt2@cornell.edu1: 10412771Sqtt2@cornell.edu j fail 10512771Sqtt2@cornell.edu 10612771Sqtt2@cornell.edu TEST_PASSFAIL 10712771Sqtt2@cornell.edu 10812771Sqtt2@cornell.edu .align 8 10912771Sqtt2@cornell.edu .global mtvec_handler 11012771Sqtt2@cornell.edumtvec_handler: 11112771Sqtt2@cornell.edu j synchronous_exception 11212771Sqtt2@cornell.edu j msip 11312771Sqtt2@cornell.edu j fail 11412771Sqtt2@cornell.edu j fail 11512771Sqtt2@cornell.edu j fail 11612771Sqtt2@cornell.edu j fail 11712771Sqtt2@cornell.edu j fail 11812771Sqtt2@cornell.edu j fail 11912771Sqtt2@cornell.edu j fail 12012771Sqtt2@cornell.edu j fail 12112771Sqtt2@cornell.edu j fail 12212771Sqtt2@cornell.edu j fail 12312771Sqtt2@cornell.edu j fail 12412771Sqtt2@cornell.edu j fail 12512771Sqtt2@cornell.edu j fail 12612771Sqtt2@cornell.edu j fail 12712771Sqtt2@cornell.edu 12812771Sqtt2@cornell.edusynchronous_exception: 12912771Sqtt2@cornell.edu li t1, CAUSE_ILLEGAL_INSTRUCTION 13012771Sqtt2@cornell.edu csrr t0, mcause 13112771Sqtt2@cornell.edu bne t0, t1, fail 13212771Sqtt2@cornell.edu csrr t0, mepc 13312771Sqtt2@cornell.edu 13412771Sqtt2@cornell.edu # Make sure mtval contains either 0 or the instruction word. 13512771Sqtt2@cornell.edu csrr t2, mbadaddr 13612771Sqtt2@cornell.edu beqz t2, 1f 13712771Sqtt2@cornell.edu lhu t3, 0(t0) 13812771Sqtt2@cornell.edu lhu t4, 2(t0) 13912771Sqtt2@cornell.edu slli t4, t4, 16 14012771Sqtt2@cornell.edu or t3, t3, t4 14112771Sqtt2@cornell.edu bne t2, t3, fail 14212771Sqtt2@cornell.edu1: 14312771Sqtt2@cornell.edu 14412771Sqtt2@cornell.edu la t1, bad2 14512771Sqtt2@cornell.edu beq t0, t1, 2f 14612771Sqtt2@cornell.edu la t1, bad3 14712771Sqtt2@cornell.edu beq t0, t1, 3f 14812771Sqtt2@cornell.edu la t1, bad4 14912771Sqtt2@cornell.edu beq t0, t1, 4f 15012771Sqtt2@cornell.edu la t1, bad5 15112771Sqtt2@cornell.edu beq t0, t1, 5f 15212771Sqtt2@cornell.edu la t1, bad6 15312771Sqtt2@cornell.edu beq t0, t1, 6f 15412771Sqtt2@cornell.edu la t1, bad7 15512771Sqtt2@cornell.edu beq t0, t1, 7f 15612771Sqtt2@cornell.edu la t1, bad8 15712771Sqtt2@cornell.edu beq t0, t1, 8f 15812771Sqtt2@cornell.edu la t1, bad9 15912771Sqtt2@cornell.edu beq t0, t1, 9f 16012771Sqtt2@cornell.edu j fail 16112771Sqtt2@cornell.edu2: 16212771Sqtt2@cornell.edu4: 16312771Sqtt2@cornell.edu6: 16412771Sqtt2@cornell.edu7: 16512771Sqtt2@cornell.edu addi t0, t0, 8 16612771Sqtt2@cornell.edu csrw mepc, t0 16712771Sqtt2@cornell.edu mret 16812771Sqtt2@cornell.edu 16912771Sqtt2@cornell.edu3: 17012771Sqtt2@cornell.edu li t1, MSTATUS_TW 17112771Sqtt2@cornell.edu csrs mstatus, t1 17212771Sqtt2@cornell.edu j 2b 17312771Sqtt2@cornell.edu 17412771Sqtt2@cornell.edu5: 17512771Sqtt2@cornell.edu li t1, MSTATUS_TVM 17612771Sqtt2@cornell.edu csrs mstatus, t1 17712771Sqtt2@cornell.edu j 2b 17812771Sqtt2@cornell.edu 17912771Sqtt2@cornell.edu8: 18012771Sqtt2@cornell.edu li t1, MSTATUS_TSR 18112771Sqtt2@cornell.edu csrs mstatus, t1 18212771Sqtt2@cornell.edu j 2b 18312771Sqtt2@cornell.edu 18412771Sqtt2@cornell.edu9: 18512771Sqtt2@cornell.edu j 2b 18612771Sqtt2@cornell.edu 18712771Sqtt2@cornell.eduRVTEST_CODE_END 18812771Sqtt2@cornell.edu 18912771Sqtt2@cornell.edu .data 19012771Sqtt2@cornell.eduRVTEST_DATA_BEGIN 19112771Sqtt2@cornell.edu 19212771Sqtt2@cornell.edu TEST_DATA 19312771Sqtt2@cornell.edu 19412771Sqtt2@cornell.eduRVTEST_DATA_END 195