Searched refs:curTick (Results 176 - 200 of 213) sorted by relevance

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/gem5/src/base/
H A Dcp_annotate.cc178 warn("Got null SM at tick %d\n", curTick());
290 warn("State machine stack not unwinding correctly at %d\n", curTick());
333 warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
702 curTick(), size, q, qBytes[qi-1]);
705 curTick(), size, q, qBytes[qi-1]);
827 an->time = curTick();
H A Dcp_annotate.hh442 warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
H A Dremote_gdb.cc365 curTick(), name(), _port);
/gem5/src/gpu-compute/
H A Dcompute_unit.cc680 curTick() + computeUnit->resp_tick_latency);
769 tlbCycles -= curTick();
855 schedule(mem_req_event, curTick() + req_tick_latency);
937 schedule(mem_req_event, curTick() + req_tick_latency);
1077 computeUnit->tlbCycles += curTick();
1231 computeUnit->schedule(mem_req_event, curTick() +
/gem5/src/dev/arm/
H A Dgeneric_timer.cc65 _resetTick = curTick();
136 curTick() + (_counterLimit - value()) * period);
H A Dsmmu_v3_transl.cc123 Tick resumeTick = curTick();
160 recvTick = curTick();
277 Tick ptwStartTick = curTick();
288 smmu.ptwTimeDist.sample(curTick() - ptwStartTick);
1238 smmu.translationTimeDist.sample(curTick() - recvTick);
H A Dhdlcd.cc233 schedule(virtRefreshEvent, (curTick() + virtRefreshRate));
H A Dgic_v2.cc827 postFiq(cpu, curTick() + intLatency);
829 postInt(cpu, curTick() + intLatency);
/gem5/src/mem/ruby/system/
H A DSequencer.cc461 curTick(), m_version, "Seq",
645 curTick(), m_version, "Seq", "Begin", "", "",
/gem5/src/cpu/simple/
H A Datomic.cc730 stall_ticks += clockEdge(syscallRetryLatency) - curTick();
768 reschedule(tickEvent, curTick() + latency, true);
/gem5/configs/splash2/
H A Dcluster.py303 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
/gem5/tests/configs/
H A Dgpu-ruby.py82 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
/gem5/util/tlm/src/
H A Dsc_master_port.cc175 assert(curTick() == sc_core::sc_time_stamp().value());
/gem5/src/mem/ruby/network/
H A DMessageBuffer.cc238 m_stall_time = curTick() - message->getTime();
/gem5/src/arch/arm/
H A Dsemihosting.cc517 return retOK(curTick() / (SimClock::Int::s / 100));
524 return retOK(timeBase + round(curTick() / SimClock::Float::s));
663 const uint64_t tick = semiTick(curTick());
H A Dintregs.hh495 curTick(), reg, mode);
/gem5/src/cpu/o3/
H A Dfetch_impl.hh711 lastIcacheStall[tid] = curTick();
1131 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
1342 instruction->fetchTick = curTick();
H A Dlsq_unit_impl.hh809 cpu->schedule(wb, curTick() + 1);
1024 curTick() - store_inst->fetchTick;
/gem5/src/mem/ruby/network/garnet2.0/
H A DNetworkInterface.cc424 name(), vnet, curTick());
/gem5/src/dev/
H A Ddma_device.cc97 device->schedule(state->completionEvent, curTick() + delay);
/gem5/src/sim/
H A Dsystem.cc467 Tick samp = curTick() - lastWorkItemStarted[p];
/gem5/src/cpu/kvm/
H A Dbase.cc169 schedule(startupEvent, curTick());
640 curEventQueue()->nextTick() - curTick() : 0);
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc749 outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick()
870 mainEventQueue[0]->schedule(event, curTick());
/gem5/src/mem/
H A Dcoherent_xbar.cc486 slavePorts[slave_port_id]->schedTimingResp(pkt, curTick() + latency);
670 slavePorts[dest_port_id]->schedTimingResp(pkt, curTick() + latency);
/gem5/src/mem/cache/
H A Dbase.cc156 owner.schedule(sendRetryEvent, curTick() + 1);
291 // ready yet (i.e. time > curTick()), we don't want to
445 Tick miss_latency = curTick() - initial_tgt->recvTime;
610 schedule(writebackTempBlockAtomicEvent, curTick());
787 return allocateMissBuffer(pkt, curTick(), false);
1007 const Tick tick = curTick() + delay;

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