/gem5/src/dev/sparc/ |
H A D | iob.cc | 47 #include "cpu/intr_control.hh" 48 #include "cpu/thread_context.hh" 68 intMan[x].cpu = 0; 99 uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; 196 intMan[index].cpu = bits(data,12,8); 198 DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index, 199 intMan[index].cpu, intMan[index].vector); 271 DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n", 272 devid, intMan[devid].cpu, intMan[devid].vector); 273 ic->post(intMan[devid].cpu, SparcIS [all...] |
/gem5/src/cpu/minor/ |
H A D | decode.hh | 50 #include "cpu/minor/buffers.hh" 51 #include "cpu/minor/cpu.hh" 52 #include "cpu/minor/dyn_inst.hh" 53 #include "cpu/minor/pipe_data.hh" 66 MinorCPU &cpu; member in class:Minor::Decode
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/gem5/src/cpu/ |
H A D | thread_context.cc | 44 #include "cpu/thread_context.hh" 50 #include "cpu/base.hh" 51 #include "cpu/quiesce_event.hh" 149 BaseCPU *cpu = getCpuPtr(); local 151 if (!cpu->params()->do_quiesce) 156 cpu->reschedule(quiesceEvent, resume, true); 158 DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume);
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H A D | base.cc | 48 #include "cpu/base.hh" 60 #include "cpu/checker/cpu.hh" 61 #include "cpu/cpuevent.hh" 62 #include "cpu/profile.hh" 63 #include "cpu/thread_context.hh" 89 cpu(_cpu), _repeatEvent(true) 92 cpu->schedule(this, curTick() + _interval); 98 Counter temp = cpu->totalOps(); 101 cpu [all...] |
H A D | thread_state.hh | 36 #include "cpu/base.hh" 37 #include "cpu/profile.hh" 38 #include "cpu/thread_context.hh" 62 ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
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/gem5/src/mem/ruby/profiler/ |
H A D | AccessTraceForAddress.hh | 51 void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
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/gem5/src/arch/mips/ |
H A D | isa.cc | 37 #include "cpu/base.hh" 38 #include "cpu/thread_context.hh" 519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) argument 526 [this, cpu]{ processCP0Event(cpu, UpdateCP0); }, 528 cpu->schedule(cp0_event, cpu->clockEdge(delay)); 533 ISA::updateCPU(BaseCPU *cpu) argument 549 haltThread(cpu->getContext(tid)); 551 restoreThread(cpu 562 processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType) argument [all...] |
H A D | utility.hh | 40 #include "cpu/static_inst.hh" 41 #include "cpu/thread_context.hh" 91 void zeroRegisters(CPU *cpu);
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/gem5/src/cpu/simple/ |
H A D | atomic.cc | 44 #include "cpu/simple/atomic.hh" 51 #include "cpu/exetrace.hh" 52 #include "cpu/utils.hh" 290 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 292 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 293 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 294 cpu->wakeup(tid); 305 for (auto &t_info : cpu->threadInfo) { 320 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 321 for (ThreadID tid = 0; tid < cpu [all...] |
/gem5/src/dev/net/ |
H A D | sinic.cc | 155 Device::prepareIO(ContextID cpu, int index) argument 168 Device::prepareRead(ContextID cpu, int index) argument 171 prepareIO(cpu, index); 209 Device::prepareWrite(ContextID cpu, int index) argument 211 prepareIO(cpu, index); 223 ContextID cpu = pkt->req->contextId(); local 229 panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d", 230 cpu, index, daddr, pkt->getAddr(), pkt->getSize()); 235 "cpu=%d vnic=%d da=%#x pa=%#x size=%d", 236 info.name, cpu, inde 308 ContextID cpu = pkt->req->contextId(); local [all...] |
H A D | sinic.hh | 267 void prepareIO(ContextID cpu, int index); 268 void prepareRead(ContextID cpu, int index); 269 void prepareWrite(ContextID cpu, int index); 270 // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result);
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/gem5/src/cpu/o3/ |
H A D | lsq_impl.hh | 52 #include "cpu/o3/cpu.hh" 53 #include "cpu/o3/lsq.hh" 64 : cpu(cpu_ptr), iewStage(iew_ptr), 107 thread[tid].init(cpu, iew_ptr, params, this, tid); 320 thread[cpu->contextToThread(senderState->contextId())] 335 thread[cpu->contextToThread(senderState->contextId())].recvTimingResp(pkt); 698 ThreadID tid = cpu->contextToThread(inst->contextId()); 699 auto cacheLineSize = cpu->cacheLineSize(); 727 req->taskId(cpu [all...] |
H A D | lsq_unit.hh | 59 #include "cpu/inst_seq.hh" 60 #include "cpu/timebuf.hh" 381 /** Schedule event for the cpu. */ 382 void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); } 384 BaseTLB* dTLB() { return cpu->dtb; } 388 O3CPU *cpu; member in class:LSQUnit 667 ThreadContext *thread = cpu->tcBase(lsqID); 675 cpu->schedule(wb, cpu->clockEdge(delay)); 758 cpu [all...] |
/gem5/configs/example/arm/ |
H A D | starter_fs.py | 101 cpu_class = cpu_types[args.cpu][0] 139 *cpu_types[args.cpu]), 210 parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), 213 parser.add_argument("--cpu-freq", type=str, default="4GHz")
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/gem5/src/arch/sparc/ |
H A D | isa.cc | 37 #include "cpu/base.hh" 38 #include "cpu/thread_context.hh" 685 BaseCPU *cpu = NULL; local 701 cpu = tc->getCpuPtr(); 702 tc_num = cpu->findContext(tc); 710 SERIALIZE_OBJPTR(cpu); 771 BaseCPU *cpu = NULL; local 776 UNSERIALIZE_OBJPTR(cpu); 777 if (cpu) { 782 tc = cpu [all...] |
/gem5/tests/configs/ |
H A D | rubytest-ruby.py | 75 # We set the testers as cpu for ruby to find the correct clock domains 77 system = System(cpu = tester) 104 # Tie the ruby tester ports to the ruby cpu read and write ports
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/gem5/src/dev/alpha/ |
H A D | backdoor.cc | 47 #include "cpu/base.hh" 48 #include "cpu/thread_context.hh" 68 system(p->system), cpu(p->cpu) 95 alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 243 assert(val > 0 && "Must not access primary cpu");
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/gem5/configs/ruby/ |
H A D | MI_example.py | 69 # First create the Ruby objects associated with this cpu 79 # number of cpu ports connected to the tester object, which 80 # is stored in system.cpu. because there is only ever one 82 # size of system.cpu; therefore if len(system.cpu) == 1 83 # we use system.cpu[0] to set the clk_domain, thereby ensuring 84 # we don't index off the end of the cpu list. 85 if len(system.cpu) == 1: 86 clk_domain = system.cpu[0].clk_domain 88 clk_domain = system.cpu[ [all...] |
H A D | MESI_Two_Level.py | 72 # First create the Ruby objects associated with this cpu 86 # number of cpu ports connected to the tester object, which 87 # is stored in system.cpu. because there is only ever one 89 # size of system.cpu; therefore if len(system.cpu) == 1 90 # we use system.cpu[0] to set the clk_domain, thereby ensuring 91 # we don't index off the end of the cpu list. 92 if len(system.cpu) == 1: 93 clk_domain = system.cpu[0].clk_domain 95 clk_domain = system.cpu[ [all...] |
H A D | MOESI_CMP_directory.py | 88 # First create the Ruby objects associated with this cpu 100 # number of cpu ports connected to the tester object, which 101 # is stored in system.cpu. because there is only ever one 103 # size of system.cpu; therefore if len(system.cpu) == 1 104 # we use system.cpu[0] to set the clk_domain, thereby ensuring 105 # we don't index off the end of the cpu list. 106 if len(system.cpu) == 1: 107 clk_domain = system.cpu[0].clk_domain 109 clk_domain = system.cpu[ [all...] |
/gem5/src/arch/arm/ |
H A D | interrupts.hh | 51 #include "cpu/thread_context.hh" 62 BaseCPU * cpu; member in class:ArmISA::Interrupts 72 cpu = _cpu; 83 Interrupts(Params * p) : SimObject(p), cpu(NULL)
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/gem5/src/cpu/kvm/ |
H A D | base.hh | 50 #include "cpu/kvm/perfevent.hh" 51 #include "cpu/kvm/timer.hh" 52 #include "cpu/kvm/vm.hh" 53 #include "cpu/base.hh" 54 #include "cpu/simple_thread.hh" 96 void takeOverFrom(BaseCPU *cpu) override; 584 : MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0) 597 /** KVM cpu pointer for finishMMIOPending() callback */ 598 BaseKvmCPU *cpu; member in class:BaseKvmCPU::KVMCpuPort
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 58 #include "cpu/base.hh" 270 cpu->wakeup(0); 278 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 282 cpu = newCPU; 283 initialApicId = cpu->cpuId(); 353 assert(cpu); 608 pendingIPIs(0), cpu(NULL),
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/gem5/src/cpu/o3/probe/ |
H A D | elastic_trace.cc | 42 #include "cpu/o3/probe/elastic_trace.hh" 47 #include "cpu/reg_class.hh" 63 cpu = dynamic_cast<FullO3CPU<O3CPUImpl>*>(params->manager); 64 fatal_if(!cpu, "Manager of %s is not of type O3CPU and thus does not "\ 70 fatal_if(cpu->numThreads > 1, "numThreads = %i, %s supports tracing for"\ 71 "single-threaded workload only", cpu->numThreads, name()); 112 cpu->comInstEventQueue[(ThreadID)0]->schedule(®EtraceListenersEvent, 122 " probe listeners", curTick(), cpu->numSimulatedInsts());
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/gem5/src/dev/arm/ |
H A D | generic_timer.cc | 315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) argument 317 CoreTimers &core(getTimers(cpu)); 421 GenericTimer::readMiscReg(int reg, unsigned cpu) argument 423 CoreTimers &core(getTimers(cpu)); 514 parent.setMiscReg(reg, cpu, val); 520 RegVal value = parent.readMiscReg(reg, cpu);
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