Searched refs:access (Results 26 - 50 of 54) sorted by relevance

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/gem5/src/mem/cache/compressors/
H A Dbdi.cc78 BDI::BDICompDataZeros::access(const int index) const function in class:BDI::BDICompDataZeros
103 BDI::BDICompDataRep::access(const int index) const function in class:BDI::BDICompDataRep
130 BDI::BDICompDataUncompressed::access(const int index) const function in class:BDI::BDICompDataUncompressed
260 BDI::BDICompDataBaseDelta<TB, TD>::access(const int index) const function in class:BDI::BDICompDataBaseDelta
342 data[i] = static_cast<const BDICompData*>(comp_data)->access(i);
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.cc356 access_t access = tlm::tlm_dmi::DMI_ACCESS_NONE; local
358 access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_READ);
360 access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_WRITE);
361 dmi_data.set_granted_access(access);
/gem5/ext/mcpat/
H A Dbus_interconnect.cc78 tdp_stats.readAc.access = bus_stats.duty_cycle;
85 rtp_stats.readAc.access = bus_stats.total_access;
H A Dlogic.cc636 tdp_stats.readAc.access = num_fu;
646 per_access_energy * tdp_stats.readAc.access + base_energy / clockRate;
651 rtp_stats.readAc.access = core_stats.fpu_accesses;
653 rtp_stats.readAc.access = core_stats.ialu_accesses;
655 rtp_stats.readAc.access = core_stats.mul_accesses;
658 rt_power.readOp.dynamic = per_access_energy * rtp_stats.readAc.access +
/gem5/src/mem/cache/
H A Dcache.hh90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
H A Dnoncoherent_cache.cc83 NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, function in class:NoncoherentCache
86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
H A Dcache.cc164 Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, function in class:Cache
189 return BaseCache::access(pkt, blk, lat, writebacks);
318 // should never be satisfying an uncacheable access as we
H A Dbase.hh210 * access functions for functional, atomic and timing snoops.
282 * The CPU-side port extends the base cache slave port with access
434 * @return The number of ticks that pass due to a tag-only access.
439 * Calculate access latency in ticks given a tag lookup latency, and
440 * whether access was a hit or miss.
445 * @return The number of ticks that pass due to a block access.
454 * @param lat The latency of the access.
458 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
501 * Performs the access specified by the request.
559 * Performs the access specifie
[all...]
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.cpp251 expect<int>(0, [=]{return access(fname, F_OK);}, "access F_OK");
252 expect<int>(0, [=]{return access(fname, R_OK);}, "access R_OK");
253 expect<int>(0, [=]{return access(fname, W_OK);}, "access W_OK");
254 // gem5's implementation of access is incorrect; it should return
256 expect<bool>(true, [=]{return access(fname, X_OK) != 0;}, "access X_OK");
/gem5/src/mem/
H A Dabstract_mem.hh117 // Backdoor to access this memory.
304 * Perform an untimed memory access and update all the state
308 * @param pkt Packet performing the access
310 void access(PacketPtr pkt);
315 * access. In addition to normal accesses this also facilitates
318 * @param pkt Packet performing the access
H A Ddramsim2.cc157 access(pkt);
212 // perform the access for writes
257 // do the actual memory access which also turns the packet into a
259 access(pkt);
263 // access already turned the packet into a response
311 // perform the actual memory access
H A Dsimple_mem.cc79 access(pkt);
H A Dphysical.cc278 PhysicalMemory::access(PacketPtr pkt) function in class:PhysicalMemory
283 m->second->access(pkt);
H A Dabstract_mem.cc331 AbstractMemory::access(PacketPtr pkt) function in class:AbstractMemory
/gem5/src/mem/qos/
H A Dmem_sink.cc95 access(pkt);
280 // Do the actual memory access which also turns the packet
282 access(pkt);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Ddirty.S33 # Set SUM=1 so user memory access is permitted
/gem5/tests/
H A Drun.py111 Python documentation for os.access().
114 if os.access(path, mode):
H A Dtests.py179 if not os.path.isfile(args.gem5) or not os.access(args.gem5, os.X_OK):
/gem5/configs/common/
H A DFileSystemConfig.py36 from os import mkdir, makedirs, getpid, listdir, stat, access
/gem5/system/alpha/console/
H A Ddbmentry.S55 addq t3,0x70,t3 # *** If offset in console alpha access struct changes
/gem5/src/cpu/testers/traffic_gen/
H A Dtraffic_gen.cc126 if (access(config_rel.c_str(), R_OK) == 0)
/gem5/src/sim/
H A Dprocess.cc438 if (access((host_path + tail).c_str(), R_OK) == 0) {
/gem5/src/mem/ruby/system/
H A DRubyPort.cc363 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
382 // The following command performs the real functional access.
390 // Do the functional access on ruby memory
411 DPRINTF(RubyPort, "Functional access %s!\n",
505 // and Flush operations access M5 physical memory.
517 // Failed SC packets don't access physical memory and thus
531 // Flush, acquire, release requests don't access physical memory
546 rs->getPhysMem()->access(pkt);
/gem5/util/minorview/
H A Dmodel.py756 if not os.access(file, os.R_OK):
1060 if not os.access(filename, os.R_OK):
/gem5/src/cpu/o3/
H A Dinst_queue_impl.hh767 issueToExecuteQueue->access(-1)->size++;
781 IssueStruct *i2e_info = issueToExecuteQueue->access(0);

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