/gem5/src/mem/cache/compressors/ |
H A D | bdi.cc | 78 BDI::BDICompDataZeros::access(const int index) const function in class:BDI::BDICompDataZeros 103 BDI::BDICompDataRep::access(const int index) const function in class:BDI::BDICompDataRep 130 BDI::BDICompDataUncompressed::access(const int index) const function in class:BDI::BDICompDataUncompressed 260 BDI::BDICompDataBaseDelta<TB, TD>::access(const int index) const function in class:BDI::BDICompDataBaseDelta 342 data[i] = static_cast<const BDICompData*>(comp_data)->access(i);
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/gem5/src/systemc/tlm_bridge/ |
H A D | tlm_to_gem5.cc | 356 access_t access = tlm::tlm_dmi::DMI_ACCESS_NONE; local 358 access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_READ); 360 access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_WRITE); 361 dmi_data.set_granted_access(access);
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/gem5/ext/mcpat/ |
H A D | bus_interconnect.cc | 78 tdp_stats.readAc.access = bus_stats.duty_cycle; 85 rtp_stats.readAc.access = bus_stats.total_access;
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H A D | logic.cc | 636 tdp_stats.readAc.access = num_fu; 646 per_access_energy * tdp_stats.readAc.access + base_energy / clockRate; 651 rtp_stats.readAc.access = core_stats.fpu_accesses; 653 rtp_stats.readAc.access = core_stats.ialu_accesses; 655 rtp_stats.readAc.access = core_stats.mul_accesses; 658 rt_power.readOp.dynamic = per_access_energy * rtp_stats.readAc.access +
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/gem5/src/mem/cache/ |
H A D | cache.hh | 90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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H A D | noncoherent_cache.cc | 83 NoncoherentCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, function in class:NoncoherentCache 86 bool success = BaseCache::access(pkt, blk, lat, writebacks);
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H A D | cache.cc | 164 Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, function in class:Cache 189 return BaseCache::access(pkt, blk, lat, writebacks); 318 // should never be satisfying an uncacheable access as we
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H A D | base.hh | 210 * access functions for functional, atomic and timing snoops. 282 * The CPU-side port extends the base cache slave port with access 434 * @return The number of ticks that pass due to a tag-only access. 439 * Calculate access latency in ticks given a tag lookup latency, and 440 * whether access was a hit or miss. 445 * @return The number of ticks that pass due to a block access. 454 * @param lat The latency of the access. 458 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 501 * Performs the access specified by the request. 559 * Performs the access specifie [all...] |
/gem5/tests/test-progs/insttest/src/riscv/ |
H A D | rv64i.cpp | 251 expect<int>(0, [=]{return access(fname, F_OK);}, "access F_OK"); 252 expect<int>(0, [=]{return access(fname, R_OK);}, "access R_OK"); 253 expect<int>(0, [=]{return access(fname, W_OK);}, "access W_OK"); 254 // gem5's implementation of access is incorrect; it should return 256 expect<bool>(true, [=]{return access(fname, X_OK) != 0;}, "access X_OK");
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/gem5/src/mem/ |
H A D | abstract_mem.hh | 117 // Backdoor to access this memory. 304 * Perform an untimed memory access and update all the state 308 * @param pkt Packet performing the access 310 void access(PacketPtr pkt); 315 * access. In addition to normal accesses this also facilitates 318 * @param pkt Packet performing the access
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H A D | dramsim2.cc | 157 access(pkt); 212 // perform the access for writes 257 // do the actual memory access which also turns the packet into a 259 access(pkt); 263 // access already turned the packet into a response 311 // perform the actual memory access
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H A D | simple_mem.cc | 79 access(pkt);
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H A D | physical.cc | 278 PhysicalMemory::access(PacketPtr pkt) function in class:PhysicalMemory 283 m->second->access(pkt);
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H A D | abstract_mem.cc | 331 AbstractMemory::access(PacketPtr pkt) function in class:AbstractMemory
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/gem5/src/mem/qos/ |
H A D | mem_sink.cc | 95 access(pkt); 280 // Do the actual memory access which also turns the packet 282 access(pkt);
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | dirty.S | 33 # Set SUM=1 so user memory access is permitted
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/gem5/tests/ |
H A D | run.py | 111 Python documentation for os.access(). 114 if os.access(path, mode):
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H A D | tests.py | 179 if not os.path.isfile(args.gem5) or not os.access(args.gem5, os.X_OK):
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/gem5/configs/common/ |
H A D | FileSystemConfig.py | 36 from os import mkdir, makedirs, getpid, listdir, stat, access
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/gem5/system/alpha/console/ |
H A D | dbmentry.S | 55 addq t3,0x70,t3 # *** If offset in console alpha access struct changes
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | traffic_gen.cc | 126 if (access(config_rel.c_str(), R_OK) == 0)
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/gem5/src/sim/ |
H A D | process.cc | 438 if (access((host_path + tail).c_str(), R_OK) == 0) {
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/gem5/src/mem/ruby/system/ |
H A D | RubyPort.cc | 363 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 382 // The following command performs the real functional access. 390 // Do the functional access on ruby memory 411 DPRINTF(RubyPort, "Functional access %s!\n", 505 // and Flush operations access M5 physical memory. 517 // Failed SC packets don't access physical memory and thus 531 // Flush, acquire, release requests don't access physical memory 546 rs->getPhysMem()->access(pkt);
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/gem5/util/minorview/ |
H A D | model.py | 756 if not os.access(file, os.R_OK): 1060 if not os.access(filename, os.R_OK):
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/gem5/src/cpu/o3/ |
H A D | inst_queue_impl.hh | 767 issueToExecuteQueue->access(-1)->size++; 781 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
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