1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Dave Greene
42 *          Steve Reinhardt
43 *          Ron Dreslinski
44 *          Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include <cstdint>
56#include <unordered_set>
57
58#include "base/types.hh"
59#include "mem/cache/base.hh"
60#include "mem/packet.hh"
61
62class CacheBlk;
63struct CacheParams;
64class MSHR;
65
66/**
67 * A coherent cache that can be arranged in flexible topologies.
68 */
69class Cache : public BaseCache
70{
71  protected:
72    /**
73     * This cache should allocate a block on a line-sized write miss.
74     */
75    const bool doFastWrites;
76
77    /**
78     * Store the outstanding requests that we are expecting snoop
79     * responses from so we can determine which snoop responses we
80     * generated and which ones were merely forwarded.
81     */
82    std::unordered_set<RequestPtr> outstandingSnoop;
83
84  protected:
85    /**
86     * Turn line-sized writes into WriteInvalidate transactions.
87     */
88    void promoteWholeLineWrites(PacketPtr pkt);
89
90    bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
91                PacketList &writebacks) override;
92
93    void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
94                            Tick request_time) override;
95
96    void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
97                             Tick forward_time,
98                             Tick request_time) override;
99
100    void recvTimingReq(PacketPtr pkt) override;
101
102    void doWritebacks(PacketList& writebacks, Tick forward_time) override;
103
104    void doWritebacksAtomic(PacketList& writebacks) override;
105
106    void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
107                            CacheBlk *blk) override;
108
109    void recvTimingSnoopReq(PacketPtr pkt) override;
110
111    void recvTimingSnoopResp(PacketPtr pkt) override;
112
113    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
114                               PacketList &writebacks) override;
115
116    Tick recvAtomic(PacketPtr pkt) override;
117
118    Tick recvAtomicSnoop(PacketPtr pkt) override;
119
120    void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
121                        bool deferred_response = false,
122                        bool pending_downgrade = false) override;
123
124    void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
125                                bool already_copied, bool pending_inval);
126
127    /**
128     * Perform an upward snoop if needed, and update the block state
129     * (possibly invalidating the block). Also create a response if required.
130     *
131     * @param pkt Snoop packet
132     * @param blk Cache block being snooped
133     * @param is_timing Timing or atomic for the response
134     * @param is_deferred Is this a deferred snoop or not?
135     * @param pending_inval Do we have a pending invalidation?
136     *
137     * @return The snoop delay incurred by the upwards snoop
138     */
139    uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
140                         bool is_timing, bool is_deferred, bool pending_inval);
141
142    M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
143
144    /**
145     * Create a CleanEvict request for the given block.
146     *
147     * @param blk The block to evict.
148     * @return The CleanEvict request for the block.
149     */
150    PacketPtr cleanEvictBlk(CacheBlk *blk);
151
152    PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
153                               bool needs_writable,
154                               bool is_whole_line_write) const override;
155
156    /**
157     * Send up a snoop request and find cached copies. If cached copies are
158     * found, set the BLOCK_CACHED flag in pkt.
159     */
160    bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
161
162  public:
163    /** Instantiates a basic cache object. */
164    Cache(const CacheParams *p);
165
166    /**
167     * Take an MSHR, turn it into a suitable downstream packet, and
168     * send it out. This construct allows a queue entry to choose a suitable
169     * approach based on its type.
170     *
171     * @param mshr The MSHR to turn into a packet and send
172     * @return True if the port is waiting for a retry
173     */
174    bool sendMSHRQueuePacket(MSHR* mshr) override;
175};
176
177#endif // __MEM_CACHE_CACHE_HH__
178