/gem5/src/cpu/kvm/ |
H A D | X86KvmCPU.py | 47 useXSave = Param.Bool(True, "Use XSave to synchronize FPU/SIMD registers")
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/gem5/src/cpu/o3/probe/ |
H A D | ElasticTrace.py | 63 traceVirtAddr = Param.Bool(False, "Set to true if virtual addresses are " \
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/gem5/src/mem/ |
H A D | MemChecker.py | 55 warn_only = Param.Bool(False, "Warn about violations only")
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H A D | XBar.py | 86 use_default_range = Param.Bool(False, "Perform address mapping for " \ 113 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \ 117 point_of_unification = Param.Bool(False, "Consider this crossbar the " \
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/gem5/src/sim/ |
H A D | System.py | 76 mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \ 88 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when " 108 kernel_addr_check = Param.Bool(True, 119 multi_thread = Param.Bool(False,
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H A D | Process.py | 46 useArchPT = Param.Bool('false', 'maintain an in-memory version of the page\ 48 kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in SE')
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/gem5/src/mem/cache/compressors/ |
H A D | Compressors.py | 45 use_more_compressors = Param.Bool(True, "True if should use all possible" \
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/gem5/src/dev/arm/ |
H A D | SMMUv3.py | 60 utlb_enable = Param.Bool(True, 'Micro TLB enable') 67 tlb_enable = Param.Bool(True, 'Main TLB enable') 71 prefetch_enable = Param.Bool(False, 73 prefetch_reserve_last_way = Param.Bool(True, 104 tlb_enable = Param.Bool(False, 'TLB enable') 111 cfg_enable = Param.Bool(True, 'Config cache enable') 118 ipa_enable = Param.Bool(False, 'IPA cache enable') 132 walk_enable = Param.Bool(True, 'Walk cache enable') 133 wc_nonfinal_enable = Param.Bool(False,
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/gem5/src/dev/net/ |
H A D | Ethernet.py | 82 is_switch = Param.Bool(False, "true if this a link in etherswitch") 83 dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op") 89 loopback = Param.Bool(True, "send packet back to the sending interface") 209 rx_filter = Param.Bool(True, "Enable Receive Filter") 211 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 212 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 213 rss = Param.Bool(False, "Receive Side Scaling") 219 dma_data_free = Param.Bool(False, "DMA of Data is free") 220 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 221 dma_no_allocate = Param.Bool(Tru [all...] |
/gem5/src/cpu/minor/ |
H A D | MinorCPU.py | 81 suppress = Param.Bool(False, "if true, this inst. is not executed by" 224 fetch2CycleInput = Param.Bool(True, 235 decodeCycleInput = Param.Bool(True, 241 executeCycleInput = Param.Bool(True, 275 executeSetTraceTimeOnCommit = Param.Bool(True, 277 executeSetTraceTimeOnIssue = Param.Bool(False, 280 executeAllowEarlyMemoryIssue = Param.Bool(True, 284 enableIdling = Param.Bool(True,
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/gem5/src/mem/ruby/structures/ |
H A D | RubyCache.py | 44 is_icache = Param.Bool(False, "is instruction only cache"); 51 resourceStalls = Param.Bool(False, "stall if there is a resource failure")
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H A D | RubyPrefetcher.py | 49 cross_page = Param.Bool(False, """True if prefetched address can be on a
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/gem5/src/dev/storage/ |
H A D | DiskImage.py | 36 read_only = Param.Bool(False, "read only image")
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.py | 43 check_flush = Param.Bool(False, "check cache flushing")
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/gem5/src/mem/cache/ |
H A D | Cache.py | 98 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 101 prefetch_on_access = Param.Bool(False, 110 sequential_access = Param.Bool(False, 127 writeback_clean = Param.Bool(False, "Writeback clean lines")
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/gem5/src/dev/ |
H A D | Device.py | 116 ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 117 update_data = Param.Bool(False, "Update the data that is returned on writes") 119 fake_mem = Param.Bool(False, 124 ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
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/gem5/src/gpu-compute/ |
H A D | X86GPUTLB.py | 65 allocationPolicy = Param.Bool(True, "Allocate on an access") 66 accessDistance = Param.Bool(False, "print accessDistance stats") 76 disableCoalescing = Param.Bool(False,"Dispable Coalescing")
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/gem5/src/arch/x86/bios/ |
H A D | IntelMP.py | 51 imcr_present = Param.Bool(True, 102 enable = Param.Bool(True, 'if this processor is usable') 103 bootstrap = Param.Bool(False, 'if this is the bootstrap processor') 132 enable = Param.Bool(True, 'if this APIC is usable') 218 subtractive_decode = Param.Bool(False, 233 add = Param.Bool(False,
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/gem5/src/dev/pci/ |
H A D | PciDevice.py | 86 BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO") 87 BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO") 88 BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO") 89 BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") 90 BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") 91 BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
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/gem5/src/cpu/trace/ |
H A D | TraceCPU.py | 81 enableEarlyExit = Param.Bool(False, "Exit when any one Trace CPU "\
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/gem5/src/cpu/testers/memtest/ |
H A D | MemTest.py | 74 suppress_func_warnings = Param.Bool(False, "Suppress warnings when "\
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/gem5/src/arch/arm/ |
H A D | ArmTLB.py | 51 is_stage2 = Param.Bool(False, "Is this object for stage 2 translation?") 70 is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
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/gem5/src/mem/cache/prefetch/ |
H A D | Prefetcher.py | 75 on_miss = Param.Bool(False, "Only notify prefetcher on misses") 76 on_read = Param.Bool(True, "Notify prefetcher on reads") 77 on_write = Param.Bool(True, "Notify prefetcher on writes") 78 on_data = Param.Bool(True, "Notify prefetcher on data accesses") 79 on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses") 80 prefetch_on_access = Param.Bool(Parent.prefetch_on_access, 82 use_virtual_addresses = Param.Bool(False, 126 queue_squash = Param.Bool(True, "Squash queued prefetch on demand access") 127 queue_filter = Param.Bool(True, "Don't queue redundant prefetches") 128 cache_snoop = Param.Bool(Fals [all...] |
/gem5/src/cpu/pred/ |
H A D | BranchPredictor.py | 47 indirectHashGHR = Param.Bool(True, "Hash branch predictor GHR") 48 indirectHashTargets = Param.Bool(True, "Hash path history targets") 143 noSkip = VectorParam.Bool([], "Vector of enabled TAGE tables") 145 speculativeHistUpdate = Param.Bool(True, 186 useSpeculation = Param.Bool(False, "Use speculation") 189 useHashing = Param.Bool(False, "Use hashing") 192 useDirectionBit = Param.Bool(False, "Use direction info") 196 restrictAllocation = Param.Bool(False, 201 optionalAgeReset = Param.Bool(True, 237 truncatePathHist = Param.Bool(Tru [all...] |
/gem5/src/arch/mips/ |
H A D | MipsSystem.py | 41 bare_iron = Param.Bool(False, "Using Bare Iron Mode?")
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