1# Copyright (c) 2013 ARM Limited
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38#
39# Authors: Nathan Binkert
40
41from m5.SimObject import SimObject
42from m5.params import *
43from m5.proxy import *
44from m5.objects.Device import DmaDevice
45from m5.objects.PciHost import PciHost
46
47class PciDevice(DmaDevice):
48    type = 'PciDevice'
49    cxx_class = 'PciDevice'
50    cxx_header = "dev/pci/device.hh"
51    abstract = True
52
53    host = Param.PciHost(Parent.any, "PCI host")
54    pci_bus = Param.Int("PCI bus")
55    pci_dev = Param.Int("PCI device number")
56    pci_func = Param.Int("PCI function code")
57
58    pio_latency = Param.Latency('30ns', "Programmed IO latency")
59    config_latency = Param.Latency('20ns', "Config read or write latency")
60
61    VendorID = Param.UInt16("Vendor ID")
62    DeviceID = Param.UInt16("Device ID")
63    Command = Param.UInt16(0, "Command")
64    Status = Param.UInt16(0, "Status")
65    Revision = Param.UInt8(0, "Device")
66    ProgIF = Param.UInt8(0, "Programming Interface")
67    SubClassCode = Param.UInt8(0, "Sub-Class Code")
68    ClassCode = Param.UInt8(0, "Class Code")
69    CacheLineSize = Param.UInt8(0, "System Cacheline Size")
70    LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
71    HeaderType = Param.UInt8(0, "PCI Header Type")
72    BIST = Param.UInt8(0, "Built In Self Test")
73
74    BAR0 = Param.UInt32(0x00, "Base Address Register 0")
75    BAR1 = Param.UInt32(0x00, "Base Address Register 1")
76    BAR2 = Param.UInt32(0x00, "Base Address Register 2")
77    BAR3 = Param.UInt32(0x00, "Base Address Register 3")
78    BAR4 = Param.UInt32(0x00, "Base Address Register 4")
79    BAR5 = Param.UInt32(0x00, "Base Address Register 5")
80    BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
81    BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
82    BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
83    BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
84    BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
85    BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
86    BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO")
87    BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO")
88    BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO")
89    BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
90    BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
91    BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
92    LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
93
94    CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
95    SubsystemID = Param.UInt16(0x00, "Subsystem ID")
96    SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
97    ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
98    CapabilityPtr = Param.UInt8(0x00, "Capability List Pointer offset")
99    InterruptLine = Param.UInt8(0x00, "Interrupt Line")
100    InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
101    MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
102    MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
103
104    # Capabilities List structures for PCIe devices
105    # PMCAP - PCI Power Management Capability
106    PMCAPBaseOffset = \
107        Param.UInt8(0x00, "Base offset of PMCAP in PCI Config space")
108    PMCAPNextCapability = \
109        Param.UInt8(0x00, "Pointer to next capability block")
110    PMCAPCapId = \
111        Param.UInt8(0x00, "Specifies this is the Power Management capability")
112    PMCAPCapabilities = \
113        Param.UInt16(0x0000, "PCI Power Management Capabilities Register")
114    PMCAPCtrlStatus = \
115        Param.UInt16(0x0000, "PCI Power Management Control and Status")
116
117    # MSICAP - Message Signaled Interrupt Capability
118    MSICAPBaseOffset = \
119        Param.UInt8(0x00, "Base offset of MSICAP in PCI Config space")
120    MSICAPNextCapability = \
121        Param.UInt8(0x00, "Pointer to next capability block")
122    MSICAPCapId = Param.UInt8(0x00, "Specifies this is the MSI Capability")
123    MSICAPMsgCtrl = Param.UInt16(0x0000, "MSI Message Control")
124    MSICAPMsgAddr = Param.UInt32(0x00000000, "MSI Message Address")
125    MSICAPMsgUpperAddr = Param.UInt32(0x00000000, "MSI Message Upper Address")
126    MSICAPMsgData = Param.UInt16(0x0000, "MSI Message Data")
127    MSICAPMaskBits = Param.UInt32(0x00000000, "MSI Interrupt Mask Bits")
128    MSICAPPendingBits = Param.UInt32(0x00000000, "MSI Pending Bits")
129
130    # MSIXCAP - MSI-X Capability
131    MSIXCAPBaseOffset = \
132        Param.UInt8(0x00, "Base offset of MSIXCAP in PCI Config space")
133    MSIXCAPNextCapability = \
134        Param.UInt8(0x00, "Pointer to next capability block")
135    MSIXCAPCapId = Param.UInt8(0x00, "Specifices this the MSI-X Capability")
136    MSIXMsgCtrl = Param.UInt16(0x0000, "MSI-X Message Control")
137    MSIXTableOffset = \
138        Param.UInt32(0x00000000, "MSI-X Table Offset and Table BIR")
139    MSIXPbaOffset = Param.UInt32(0x00000000, "MSI-X PBA Offset and PBA BIR")
140
141    # PXCAP - PCI Express Capability
142    PXCAPBaseOffset = \
143        Param.UInt8(0x00, "Base offset of PXCAP in PCI Config space")
144    PXCAPNextCapability = Param.UInt8(0x00, "Pointer to next capability block")
145    PXCAPCapId = Param.UInt8(0x00, "Specifies this is the PCIe Capability")
146    PXCAPCapabilities = Param.UInt16(0x0000, "PCIe Capabilities")
147    PXCAPDevCapabilities = Param.UInt32(0x00000000, "PCIe Device Capabilities")
148    PXCAPDevCtrl = Param.UInt16(0x0000, "PCIe Device Control")
149    PXCAPDevStatus = Param.UInt16(0x0000, "PCIe Device Status")
150    PXCAPLinkCap = Param.UInt32(0x00000000, "PCIe Link Capabilities")
151    PXCAPLinkCtrl = Param.UInt16(0x0000, "PCIe Link Control")
152    PXCAPLinkStatus = Param.UInt16(0x0000, "PCIe Link Status")
153    PXCAPDevCap2 = Param.UInt32(0x00000000, "PCIe Device Capabilities 2")
154    PXCAPDevCtrl2 = Param.UInt32(0x00000000, "PCIe Device Control 2")
155