/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.cc | 103 CacheMemory::addressToCacheSet(Addr address) const 113 CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const 129 Addr tag) const 142 Addr 145 Addr tmp(0); 163 CacheMemory::tryCacheAccess(Addr address, RubyRequestType type, 190 CacheMemory::testCacheAccess(Addr address, RubyRequestType type, 214 CacheMemory::isTagPresent(Addr address) const 233 CacheMemory::cacheAvail(Addr address) const 255 CacheMemory::allocate(Addr addres [all...] |
/gem5/src/dev/virtio/ |
H A D | base.hh | 335 void setAddress(Addr address); 341 Addr getAddress() const { return _address; } 436 static const Addr ALIGN_BITS = 12; 437 static const Addr ALIGN_SIZE = 1 << ALIGN_BITS; 458 Addr _address; 490 void setAddress(Addr addr) { _base = addr; } 543 Addr _base; 670 virtual void readConfig(PacketPtr pkt, Addr cfgOffset); 685 virtual void writeConfig(PacketPtr pkt, Addr cfgOffset); 714 void readConfigBlob(PacketPtr pkt, Addr cfgOffse [all...] |
/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.cc | 111 AbstractController::stallBuffer(MessageBuffer* buf, Addr addr) 125 AbstractController::wakeUpBuffers(Addr addr) 146 AbstractController::wakeUpAllBuffers(Addr addr) 206 AbstractController::blockOnQueue(Addr addr, MessageBuffer* port) 213 AbstractController::isBlocked(Addr addr) const 219 AbstractController::unblock(Addr addr) 228 AbstractController::isBlocked(Addr addr) 240 AbstractController::queueMemoryRead(const MachineID &id, Addr addr, 264 AbstractController::queueMemoryWrite(const MachineID &id, Addr addr, 289 AbstractController::queueMemoryWritePartial(const MachineID &id, Addr add [all...] |
/gem5/src/mem/ |
H A D | request.hh | 295 setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 314 Addr _paddr; 375 Addr _vaddr; 386 Addr _pc; 409 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, 427 Request(Addr paddr, unsigned size, Flags flags, MasterID mid) 437 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) 447 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time, 448 Addr pc) 459 Request(uint64_t asid, Addr vadd [all...] |
H A D | dramsim2.hh | 117 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads; 118 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
|
H A D | CommMonitor.py | 100 read_addr_mask = Param.Addr(MaxAddr, "Address mask for read address") 101 write_addr_mask = Param.Addr(MaxAddr, "Address mask for write address")
|
/gem5/src/arch/sparc/ |
H A D | system.hh | 126 Addr 127 fixFuncEventAddr(Addr addr) override
|
/gem5/src/dev/arm/ |
H A D | timer_a9global.hh | 132 void read(PacketPtr pkt, Addr daddr); 135 void write(PacketPtr pkt, Addr daddr);
|
H A D | timer_sp804.hh | 119 void read(PacketPtr pkt, Addr daddr); 122 void write(PacketPtr pkt, Addr daddr);
|
H A D | smmu_v3_proc.hh | 114 void doRead(Yield &yield, Addr addr, void *ptr, size_t size); 115 void doWrite(Yield &yield, Addr addr, const void *ptr, size_t size);
|
H A D | a9scu.cc | 58 Addr daddr = pkt->getAddr() - pioAddr; 95 Addr daddr = pkt->getAddr() - pioAddr;
|
/gem5/src/arch/arm/linux/ |
H A D | system.hh | 130 DumpStatsPCEvent(PCEventQueue *q, const std::string &desc, Addr addr) 143 DumpStatsPCEvent64(PCEventQueue *q, const std::string &desc, Addr addr)
|
/gem5/src/arch/sparc/insts/ |
H A D | blockmem.cc | 38 BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const 63 BlockMemImmMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
H A D | mem.cc | 39 Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const 66 MemImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
H A D | nop.cc | 59 std::string generateDisassembly(Addr pc, 65 std::string Nop::generateDisassembly(Addr pc,
|
/gem5/src/cpu/ |
H A D | static_inst.cc | 61 generateDisassembly(Addr pc, const SymbolTable *symtab) const override 123 StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
|
H A D | inst_pb_trace.hh | 123 * @param pc for the PC Addr 133 void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
|
/gem5/src/arch/riscv/ |
H A D | decoder.cc | 53 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 82 Decoder::decode(ExtMachInst mach_inst, Addr addr)
|
/gem5/src/dev/x86/ |
H A D | i8237.cc | 40 Addr offset = pkt->getAddr() - pioAddr; 75 Addr offset = pkt->getAddr() - pioAddr;
|
/gem5/src/mem/cache/tags/indexing_policies/ |
H A D | base.cc | 98 Addr 99 BaseIndexingPolicy::extractTag(const Addr addr) const
|
/gem5/src/arch/x86/ |
H A D | mmapped_ipr.hh | 63 Addr offset = pkt->getAddr() & mask(3); 80 Addr offset = pkt->getAddr() & mask(3);
|
/gem5/src/base/loader/ |
H A D | hex_file.cc | 68 Addr MemAddr; 84 HexFile::parseLine(char *Str, Addr *A, uint32_t *D)
|
/gem5/src/dev/storage/ |
H A D | simple_disk.cc | 64 SimpleDisk::read(Addr addr, baddr_t block, int count) const 83 SimpleDisk::write(Addr addr, baddr_t block, int count)
|
/gem5/src/mem/cache/ |
H A D | write_queue_entry.hh | 127 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, 183 bool matchBlockAddr(const Addr addr, const bool is_secure) const override;
|
/gem5/src/arch/arm/insts/ |
H A D | misc64.hh | 57 Addr pc, const SymbolTable *symtab) const override; 76 Addr pc, const SymbolTable *symtab) const override; 95 Addr pc, const SymbolTable *symtab) const override; 107 Addr pc, const SymbolTable *symtab) const override; 167 Addr pc, const SymbolTable *symtab) const override; 185 Addr pc, const SymbolTable *symtab) const override; 203 Addr pc, const SymbolTable *symtab) const override; 231 Addr pc, const SymbolTable *symtab) const override;
|