1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * Write queue entry
47 */
48
49#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
50#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
51
52#include <cassert>
53#include <iosfwd>
54#include <list>
55#include <string>
56
57#include "base/printable.hh"
58#include "base/types.hh"
59#include "mem/cache/queue_entry.hh"
60#include "mem/packet.hh"
61#include "sim/core.hh"
62
63class BaseCache;
64
65/**
66 * Write queue entry
67 */
68class WriteQueueEntry : public QueueEntry, public Printable
69{
70
71    /**
72     * Consider the queues friends to avoid making everything public.
73     */
74    template<typename Entry>
75    friend class Queue;
76    friend class WriteQueue;
77
78  public:
79    class TargetList : public std::list<Target> {
80
81      public:
82
83        TargetList() {}
84        void add(PacketPtr pkt, Tick readyTime, Counter order);
85        bool trySatisfyFunctional(PacketPtr pkt);
86        void print(std::ostream &os, int verbosity,
87                   const std::string &prefix) const;
88    };
89
90    /** A list of write queue entriess. */
91    typedef std::list<WriteQueueEntry *> List;
92    /** WriteQueueEntry list iterator. */
93    typedef List::iterator Iterator;
94
95    bool sendPacket(BaseCache &cache) override;
96
97  private:
98
99    /**
100     * Pointer to this entry on the ready list.
101     * @sa MissQueue, WriteQueue::readyList
102     */
103    Iterator readyIter;
104
105    /**
106     * Pointer to this entry on the allocated list.
107     * @sa MissQueue, WriteQueue::allocatedList
108     */
109    Iterator allocIter;
110
111    /** List of all requests that match the address */
112    TargetList targets;
113
114  public:
115
116    /** A simple constructor. */
117    WriteQueueEntry() {}
118
119    /**
120     * Allocate a miss to this entry.
121     * @param blk_addr The address of the block.
122     * @param blk_size The number of bytes to request.
123     * @param pkt The original write.
124     * @param when_ready When should the write be sent out.
125     * @param _order The logical order of this write.
126     */
127    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
128                  Tick when_ready, Counter _order);
129
130
131    /**
132     * Mark this entry as free.
133     */
134    void deallocate();
135
136    /**
137     * Returns the current number of allocated targets.
138     * @return The current number of allocated targets.
139     */
140    int getNumTargets() const
141    { return targets.size(); }
142
143    /**
144     * Returns true if there are targets left.
145     * @return true if there are targets
146     */
147    bool hasTargets() const { return !targets.empty(); }
148
149    /**
150     * Returns a reference to the first target.
151     * @return A pointer to the first target.
152     */
153    Target *getTarget() override
154    {
155        assert(hasTargets());
156        return &targets.front();
157    }
158
159    /**
160     * Pop first target.
161     */
162    void popTarget()
163    {
164        targets.pop_front();
165    }
166
167    bool trySatisfyFunctional(PacketPtr pkt);
168
169    /**
170     * Prints the contents of this MSHR for debugging.
171     */
172    void print(std::ostream &os,
173               int verbosity = 0,
174               const std::string &prefix = "") const override;
175    /**
176     * A no-args wrapper of print(std::ostream...)  meant to be
177     * invoked from DPRINTFs avoiding string overheads in fast mode
178     *
179     * @return string with mshr fields
180     */
181    std::string print() const;
182
183    bool matchBlockAddr(const Addr addr, const bool is_secure) const override;
184    bool matchBlockAddr(const PacketPtr pkt) const override;
185    bool conflictAddr(const QueueEntry* entry) const override;
186};
187
188#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
189