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/gem5/src/arch/arm/
H A Dsystem.hh11234:c273990ed9bf Thu Dec 03 18:53:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> arm: Add support for automatic boot loader selection

Add support for automatically selecting a boot loader that matches the
guest system's kernel. Instead of accepting a single boot loader, the
ArmSystem class now accepts a vector of boot loaders. When
initializing a system, the we now look for the first boot loader with
an architecture that matches the kernel.

This changeset makes it possible to use the same system for both
64-bit and 32-bit kernels.
H A Dtable_walker.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
H A Dtlb.hh6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
H A Dtlb.cc10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/cpu/kvm/
H A Dbase.hh9892:0063c7dd18ec Mon Sep 30 03:53:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Add support for thread-specific instruction events

Instruction events are currently ignored when executing in KVM. This
changeset adds support for triggering KVM exits based on instruction
counts using hardware performance counters. Depending on the
underlying performance counter implementation, there might be some
inaccuracies due to instructions being counted in the host kernel when
entering/exiting KVM.

Due to limitations/bugs in Linux's performance counter interface, we
can't reliably change the period of an overflow counter. We work
around this issue by detaching and reattaching the counter if we need
to reconfigure it.
H A Dbase.cc9892:0063c7dd18ec Mon Sep 30 03:53:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> kvm: Add support for thread-specific instruction events

Instruction events are currently ignored when executing in KVM. This
changeset adds support for triggering KVM exits based on instruction
counts using hardware performance counters. Depending on the
underlying performance counter implementation, there might be some
inaccuracies due to instructions being counted in the host kernel when
entering/exiting KVM.

Due to limitations/bugs in Linux's performance counter interface, we
can't reliably change the period of an overflow counter. We work
around this issue by detaching and reattaching the counter if we need
to reconfigure it.
/gem5/src/mem/
H A Dcoherent_xbar.cc11196:53d4f7e452d6 Fri Nov 06 03:26:00 EST 2015 Ali Jafri <ali.jafri@arm.com> mem: Avoid unnecessary snoops on writebacks and clean evictions

This patch optimises the handling of writebacks and clean evictions
when using a snoop filter. Instead of snooping into the caches to
determine if the block is cached or not, simply set the status based
on the snoop-filter result.
/gem5/src/mem/ruby/system/
H A DDMASequencer.cc11778:dccdf4e12a0b Tue Dec 20 11:53:00 EST 2016 Tony Gutierrez <anthony.gutierrez@amd.com> ruby: fix typo in DMASequencer::ackCallback()
H A DSequencer.hh9598:a58b28c17d7f Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.
/gem5/src/base/stats/
H A Dtext.cc7504:ad631c296c9b Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> stats: cleanup a few small problems in stats
/gem5/src/sim/
H A Dsim_object.hh3202:c095cfd0da96 Wed Oct 11 18:53:00 EDT 2006 Lisa Hsu <hsul@eecs.umich.edu> since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.

src/python/m5/SimObject.py:
now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
need this conversion now.
src/sim/sim_object.hh:
put the enum back into SimObject.
src/sim/system.hh:
memoryMode is now a part of SimObject, need the ::'s
H A Dsystem.hh9855:a317086a3e19 Thu Sep 05 13:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> sim: Fix clang warning for unused variable

This patch ensures the NULL ISA can build without causing issues with
an unused variable.
3202:c095cfd0da96 Wed Oct 11 18:53:00 EDT 2006 Lisa Hsu <hsul@eecs.umich.edu> since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.

src/python/m5/SimObject.py:
now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
need this conversion now.
src/sim/sim_object.hh:
put the enum back into SimObject.
src/sim/system.hh:
memoryMode is now a part of SimObject, need the ::'s
H A Dsyscall_emul.cc6687:9e2f25dcf8c8 Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Zero out memory that already exists during the brk system call.

Glibc often assumes that memory it receives from the kernel after a brk
system call will contain only zeros. This is important during a calloc,
because it won't clear the new memory itself. In the simulator, if the
new page exists, it will be cleared using this patch, to mimic the kernel's
functionality.
6685:af13eb1b7f81 Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Implementation of the ftruncate64 system call.
/gem5/src/base/
H A DSConscript12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/cpu/simple/
H A Dtiming.cc12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
6973:a123bd350935 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> BaseDynInst: Make the TLB translation timing instead of atomic.

This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.

The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
4022:c422464ca16e Wed Feb 07 13:53:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
3170:37fd1e73f836 Sun Oct 08 13:53:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
H A Datomic.cc12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
4022:c422464ca16e Wed Feb 07 13:53:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
3170:37fd1e73f836 Sun Oct 08 13:53:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
H A Dbase.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA.
/gem5/src/arch/sparc/isa/
H A Ddecoder.isa12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
3279:cf42adf4588f Mon Oct 16 15:53:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Changed how floating point register numbers are decoded to fit with the spec.
/gem5/configs/example/
H A Dfs.py12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
12079:a5cc6df83fcf Thu Feb 23 15:53:00 EST 2017 Gedare Bloom <gedare@rtems.org> configs, arm: add option to enable security extensions

Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3264
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/cpu/
H A Dsimple_thread.hh9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA.
2862:7bc3562e6405 Thu Jul 06 17:53:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Various serialization changes to make it possible for the O3CPU to checkpoint.

src/arch/alpha/regfile.hh:
Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
Move common serialization code into ThreadState.
/gem5/src/mem/cache/
H A Dcache.hh13948:f8666d4d5855 Thu Apr 18 09:53:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Remove writebacks packet list

Previously all atomic writebacks concerned a single block,
therefore, when a block was evicted, no other block would be
pending eviction. With sector tags (and compression),
however, a single replacement can generate many evictions.

This can cause problems, since a writeback that evicts a block
may evict blocks in the lower cache. If one of these conflict
with one of the blocks pending eviction in the higher level, the
snoop must inform it to the lower level. Since atomic mode does
not have a writebuffer, this kind of conflict wouldn't be noticed.

Therefore, instead of evicting multiple blocks at once, we
do it one by one.

Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
3861:3b35b0f0b6a9 Tue Dec 19 00:53:00 EST 2006 Steve Reinhardt <stever@eecs.umich.edu> No need to template prefetcher on cache TagStore type.
/gem5/src/cpu/o3/
H A Diew_impl.hh8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model.

Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
3221:669a04468c0d Sun Oct 08 00:53:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug.

src/cpu/o3/commit_impl.hh:
Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
Deallocate and activate threads properly. Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
More debug output.
src/cpu/o3/lsq_unit_impl.hh:
Fixup store conditional handling (still a bit of a hack, but works now).

Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
Deallocate context now records if the context should be fully removed.
H A Dfetch.hh9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA.
2757:58e3a66e72f7 Fri Jun 16 17:53:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
H A Dthread_state.hh10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis

Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.

Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
/gem5/configs/common/
H A DSimulation.py8724:7b4d80b26e35 Thu Jan 26 14:53:00 EST 2012 Ronald Dreslinski <rdreslin@umich.edu> configs: A more realistic configuration of an ARM-like processor

Completed in 490 milliseconds

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