Searched hist:2015 (Results 926 - 950 of 1505) sorted by relevance
/gem5/src/arch/power/ | ||
H A D | pagetable.hh | 10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
H A D | pagetable.cc | 10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
/gem5/src/mem/slicc/ast/ | ||
H A D | LocalVariableAST.py | 10966:198726a3c723 Mon Jul 20 10:15:00 EDT 2015 David Hashe <david.hashe@amd.com> slicc: fix missing inline function in LocalVariableAST |
/gem5/src/base/ | ||
H A D | inifile.hh | 11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. |
H A D | debug.cc | 11153:20bbfe5b2b86 Wed Sep 30 16:21:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> base: remove Trace::enabled flag The DTRACE() macro tests both Trace::enabled and the specific flag. This change uses the same administrative interface for enabling/disabling tracing, but masks the SimpleFlags settings directly. This eliminates a load for every DTRACE() test, e.g. DPRINTF. |
/gem5/src/arch/alpha/ | ||
H A D | pagetable.cc | 10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
/gem5/src/arch/mips/ | ||
H A D | pagetable.cc | 10905:a6ca6831e775 Tue Jul 07 04:51:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Refactor the serialization base class Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
H A D | decoder.hh | 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
/gem5/src/cpu/minor/ | ||
H A D | func_unit.cc | 11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues This patch adds explicit overrides as this is now required when using "-Wall" with clang >= 3.5, the latter now part of the most recent XCode. The patch consequently removes "virtual" for those methods where "override" is added. The latter should be enough of an indication. As part of this patch, a few minor issues that clang >= 3.5 complains about are also resolved (unused methods and variables). |
/gem5/src/sim/ | ||
H A D | sub_system.cc | 11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch. |
H A D | sub_system.hh | 11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch. |
/gem5/src/sim/power/ | ||
H A D | thermal_domain.cc | 11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch. |
H A D | SConscript | 11420:b48c0ba4f524 Tue May 12 05:26:00 EDT 2015 David Guillen Fandos <david.guillen@arm.com> sim: Adding thermal model support This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch. |
/gem5/tests/configs/ | ||
H A D | realview-switcheroo-full.py | 10947:6d86c48f7806 Thu Jul 30 05:16:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> tests: Add Minor to the ARM full switcheroo tests Add the Minor CPU to the RealView and RealView64 full switcheroo tests. |
H A D | tgen-dram-ctrl.py | 10720:67b3e74de9ae Mon Mar 02 04:00:00 EST 2015 Andreas Hansson <andreas.hansson@arm.com> mem: Move crossbar default latencies to subclasses This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden. |
H A D | o3-timing-mt.py | 11156:a37dda0f0202 Mon Oct 05 14:13:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update SMT tests to correctly configure CPUs The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. |
/gem5/ | ||
H A D | .hgignore | 11206:2375b33bddc6 Fri Nov 13 17:03:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> misc: ignore object files and static libs in util/m5 |
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/ | ||
H A D | simerr | 11245:1c5102c0a7a9 Fri Dec 04 19:11:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to reflect changes to PCI handling |
/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/ | ||
H A D | simerr | 10798:74e3c7359393 Wed Apr 22 23:22:00 EDT 2015 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for previous changeset Very small differences in IQ-specific O3 stats. |
/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/ | ||
H A D | simerr | 10798:74e3c7359393 Wed Apr 22 23:22:00 EDT 2015 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for previous changeset Very small differences in IQ-specific O3 stats. |
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 11219:b65d4e878ed2 Mon Nov 16 06:08:00 EST 2015 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent chagnesets 11023:97cf7ba82f0c Fri Aug 14 02:19:00 EDT 2015 Joel Hestness <jthestness@gmail.com> stats: Bump for MessageBuffer, cache latency changes 10892:bd37e25fb3b7 Fri Jul 03 10:15:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected. |
/gem5/src/arch/x86/ | ||
H A D | decoder_tables.cc | 10924:d02e9c239892 Fri Jul 17 12:31:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> x86: decode instructions with vex prefix This patch updates the x86 decoder so that it can decode instructions with vex prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3. Note that none of the instructions have been implemented yet. The implementations would be provided in due course of time. |
/gem5/src/mem/ruby/network/ | ||
H A D | Network.cc | 11113:5a2e1b1b5c43 Wed Sep 16 13:10:00 EDT 2015 Joe Gross <joe.gross@amd.com> ruby: fix message buffer init order The recent changes to make MessageBuffers SimObjects required them to be initialized in a particular order, which could break some protocols. Fix this by calling initNetQueues on the external nodes of each external link in the constructor of Network. This patch also refactors the duplicated code for checking network allocation and setting net queues (which are called by initNetQueues) from the simple and garnet networks to be in Network. 11108:6342ddf6d733 Wed Sep 16 00:03:00 EDT 2015 David Hashe <david.hashe@amd.com> ruby: rename System.{hh,cc} to RubySystem.{hh,cc} The eventual aim of this change is to pass RubySystem pointers through to objects generated from the SLICC protocol code. Because some of these objects need to dereference their RubySystem pointers, they need access to the System.hh header file. In src/mem/ruby/SConscript, the MakeInclude function creates single-line header files in the build directory that do nothing except include the corresponding header file from the source tree. However, SLICC also generates a list of header files from its symbol table, and writes it to mem/protocol/Types.hh in the build directory. This code assumes that the header file name is the same as the class name. The end result of this is the many of the generated slicc files try to include RubySystem.hh, when the file they really need is System.hh. The path of least resistence is just to rename System.hh to RubySystem.hh. 11064:386a5200e298 Sun Aug 30 01:24:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: drop member m_in_use This member indicates whether or not a particular virtual network is in use. Instead of having a default big value for the number of virtual networks and then checking whether a virtual network is in use, the next patch removes the default value and the protocol configuration file would now specify the number of virtual networks it requires. Additionally, the patch also refactors some of the code used for computing the virtual channel next in the round robin order. 10918:dd3ab1f109ad Fri Jul 10 17:05:00 EDT 2015 Brandon Potter <brandon.potter@amd.com> ruby: replace g_ruby_start with per-RubySystem m_start_cycle This patch begins the process of removing global variables from the Ruby source with the goal of eventually allowing users to create multiple Ruby instances in a single simulation. Currently, users cannot do so because several global variables and static members are referenced by the RubySystem object in a way that assumes that there will only ever be a single RubySystem. These need to be replaced with per-RubySystem equivalents. This specific patch replaces the global var g_ruby_start, which is used to calculate throughput statistics for Throttles in simple networks and links in Garnet networks, with a RubySystem instance var m_start_cycle. |
/gem5/src/dev/storage/ | ||
H A D | ide_disk.cc | 11264:dc389d2d2f79 Thu Dec 10 05:35:00 EST 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Move storage devices to src/dev/storage/ Move the IDE controller and the disk implementations to src/dev/storage. |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | RubySlicc_Util.hh | 11209:d5a7a4da9f63 Fri Nov 13 17:30:00 EST 2015 Tony Gutierrez <anthony.gutierrez@amd.com> slicc: fixes for the Address to Addr changeset (11025) misc changes now that Address has become Addr including int to address util function 11208:fa3e56b6e0b6 Fri Nov 13 17:30:00 EST 2015 Joe Gross <joseph.gross@amd.com> ruby: add BoolVec The BoolVec typedef and insertion operator overload function simplify usage of vectors of type bool 11025:4872dbdea907 Fri Aug 14 01:04:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system. 10956:19515f842044 Mon Jul 20 10:15:00 EDT 2015 Brad Beckmann <Brad.Beckmann@amd.com> ruby: re-added the addressToInt slicc interface function This helper function is very useful converting address offsets to integers that can be used for protocol specific destination mapping. |
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