Searched hist:2014 (Results 1076 - 1100 of 1681) sorted by relevance
/gem5/src/cpu/pred/ | ||
H A D | bi_mode.cc | 10335:1b627a6ddac0 Wed Sep 03 07:42:00 EDT 2014 Dam Sunwoo <dam.sunwoo@arm.com> cpu: fix bimodal predictor to use correct global history reg A small bug in the bimodal predictor caused significant degradation in performance on some benchmarks. This was caused by using the wrong globalHistoryReg during the update phase. This patches fixes the bug and brings the performance to normal level. 10244:d2deb51a4abf Mon Jun 30 13:50:00 EDT 2014 Anthony Gutierrez <atgutier@umich.edu> cpu: implement a bi-mode branch predictor |
/gem5/src/dev/arm/ | ||
H A D | vgic.cc | 10565:23593fdaadcd Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Remove redundant Packet::allocate calls This patch cleans up the packet memory allocation confusion. The data is always allocated at the requesting side, when a packet is created (or copied), and there is never a need for any device to allocate any space if it is merely responding to a paket. This behaviour is in line with how SystemC and TLM works as well, thus increasing interoperability, and matching established conventions. The redundant calls to Packet::allocate are removed, and the checks in the function are tightened up to make sure data is only ever allocated once. There are still some oddities in the packet copy constructor where we copy the data pointer if it is static (without ownership), and allocate new space if the data is dynamic (with ownership). The latter is being worked on further in a follow-on patch. 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
/gem5/configs/ruby/ | ||
H A D | MOESI_CMP_token.py | 10529:05b5a6cf3521 Thu Nov 06 06:42:00 EST 2014 Marc Orr <morr@cs.wisc.edu> x86 isa: This patch attempts an implementation at mwait. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10300:ed3816dae6d5 Mon Sep 01 17:55:00 EDT 2014 Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu> ruby: Fixes clock domains in configuration files This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10116:d61a59beb670 Mon Mar 17 18:40:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: remove piobus from protocols This patch removes the piobus from the protocol config files. The ports are now connected to the piobus in the Ruby.py file. 10092:c0db268f811b Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: correct errors in changeset 4eec7bdde5b0 Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols. 10006:8fa94dcfd545 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove cntrl_id from python config scripts. |
H A D | MOESI_CMP_directory.py | 10529:05b5a6cf3521 Thu Nov 06 06:42:00 EST 2014 Marc Orr <morr@cs.wisc.edu> x86 isa: This patch attempts an implementation at mwait. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10300:ed3816dae6d5 Mon Sep 01 17:55:00 EDT 2014 Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu> ruby: Fixes clock domains in configuration files This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10116:d61a59beb670 Mon Mar 17 18:40:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: remove piobus from protocols This patch removes the piobus from the protocol config files. The ports are now connected to the piobus in the Ruby.py file. 10092:c0db268f811b Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: correct errors in changeset 4eec7bdde5b0 Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols. 10006:8fa94dcfd545 Sat Jan 04 01:03:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove cntrl_id from python config scripts. |
H A D | Ruby.py | 10551:d60a9bb99038 Sun Nov 23 21:00:00 EST 2014 Steve Reinhardt <steve.reinhardt@amd.com> Backed out prior changeset f9fb64a72259 Back out use of importlib to avoid implicitly creating dependency on Python 2.7. 10550:f9fb64a72259 Sun Nov 23 08:55:00 EST 2014 Gabe Black <gabeblack@google.com> config: ruby: Get rid of an "eval" and an "exec" operating on generated code. We can get the same result using importlib. 10529:05b5a6cf3521 Thu Nov 06 06:42:00 EST 2014 Marc Orr <morr@cs.wisc.edu> x86 isa: This patch attempts an implementation at mwait. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10525:77787650cbbc Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: provide a backing store Ruby's functional accesses are not guaranteed to succeed as of now. While this is not a problem for the protocols that are currently in the mainline repo, it seems that coherence protocols for gpus rely on a backing store to supply the correct data. The aim of this patch is to make this backing store configurable i.e. it comes into play only when a particular option: --access-backing-store is invoked. The backing store has been there since M5 and GEMS were integrated. The only difference is that earlier the system used to maintain the backing store and ruby's copy was write-only. Sometime last year, we moved to data being supplied supplied by ruby in SE mode simulations. And now we have patches on the reviewboard, which remove ruby's copy of memory altogether and rely completely on the system's memory to supply data. This patch adds back a SimpleMemory member to RubySystem. This member is used only if the option: access-backing-store is set to true. By default, the memory would not be accessed. 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10122:1268f1fd2714 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: garnet: convert network interfaces into clocked objects This helps in configuring the network interfaces from the python script and these objects no longer rely on the network object for the timing information. 10120:f5ceb3c3edb6 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: rename _cpu_ruby_ports to _cpu_ports 10118:5e1f04b4d5e4 Thu Mar 20 09:03:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: remove ruby_fs.py The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | ldr64.isa | 10346:d96b61d843b2 Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> arm: Make memory ops work on 64bit/128-bit quantities Multiple instructions assume only 32-bit load operations are available, this patch increases load sizes to 64-bit or 128-bit for many load pair and load multiple instructions. 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
/gem5/src/cpu/minor/ | ||
H A D | decode.cc | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/dev/virtio/ | ||
H A D | base.hh | 10559:62f5f7363197 Mon Nov 24 09:03:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Another round of static analysis fixups Mostly addressing uninitialised members. 10388:a26a20060ba3 Sat Sep 20 17:17:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> dev, pci: Implement basic VirtIO support This patch adds support for VirtIO over the PCI bus. It does so by providing the following new SimObjects: * VirtIODeviceBase - Abstract base class for VirtIO devices. * PciVirtIO - VirtIO PCI transport interface. A VirtIO device is hooked up to the guest system by adding a PciVirtIO device to the PCI bus and connecting it to a VirtIO device using the vio parameter. New VirtIO devices should inherit from VirtIODevice base and implementing one or more VirtQueues. The VirtQueues are usually device-specific and all derive from the VirtQueue class. Queues must be registered with the base class from the constructor since the device assumes that the number of queues stay constant. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | base.cc | 10626:7982e539d003 Tue Dec 23 09:31:00 EST 2014 Curtis Dunham <Curtis.Dunham@arm.com> mem: Hide WriteInvalidate requests from prefetchers Without this tweak, a prefetcher will happily prefetch data that will promptly be invalidated and overwritten by a WriteInvalidate. 10623:b9646f4546ad Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Rework the structuring of the prefetchers Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure. 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. 10360:919c02740209 Tue Sep 09 04:36:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Fix a number of unitialised variables and members Static analysis unearther a bunch of uninitialised variables and members, and this patch addresses the problem. In all cases these omissions seem benign in the end, but at least fixing them means less false positives next time round. 10318:98771a936b61 Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Cleanup unused ISA traits constants This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), aligning the use of int vs Addr etc. The patch also removes the duplication of PageBytes/PageShift and VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical values and the latter has been removed. 10052:5bb8e054456b Thu Jan 30 00:21:00 EST 2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com>, Amin Farmahini <aminfar@gmail.com> mem: prefetcher: add options, support for unaligned addresses This patch extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean). 10028:fb8c44de891a Fri Jan 24 16:29:00 EST 2014 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> mem: Add support for a security bit in the memory system This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses. 10024:fc10e1f9f124 Fri Jan 24 16:29:00 EST 2014 Dam Sunwoo <dam.sunwoo@arm.com> mem: per-thread cache occupancy and per-block ages This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump. |
H A D | base.hh | 10623:b9646f4546ad Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Rework the structuring of the prefetchers Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure. 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. 10360:919c02740209 Tue Sep 09 04:36:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Fix a number of unitialised variables and members Static analysis unearther a bunch of uninitialised variables and members, and this patch addresses the problem. In all cases these omissions seem benign in the end, but at least fixing them means less false positives next time round. 10052:5bb8e054456b Thu Jan 30 00:21:00 EST 2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com>, Amin Farmahini <aminfar@gmail.com> mem: prefetcher: add options, support for unaligned addresses This patch extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean). 10028:fb8c44de891a Fri Jan 24 16:29:00 EST 2014 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> mem: Add support for a security bit in the memory system This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses. |
/gem5/src/arch/arm/ | ||
H A D | pagetable.hh | 10558:426665ec11a9 Sun Nov 23 21:01:00 EST 2014 Alexandru Dutu <alexandru.dutu@amd.com> mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes. 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | misc64.isa | 10184:bbfa3152bdea Fri May 09 18:58:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> arch: remove inline specifiers on all inst constrs, all ISAs With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions. 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
/gem5/src/arch/arm/insts/ | ||
H A D | mem64.hh | 10537:47fe87b0cf97 Fri Nov 14 03:53:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixes based on UBSan and static analysis Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32) Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
/gem5/src/python/m5/util/ | ||
H A D | dot_writer.py | 10405:7a618c07e663 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. 10176:266db8ff9ae8 Wed Apr 23 05:18:00 EDT 2014 Sascha Bischoff <sascha.bischoff@arm.com> misc: Proper type check and import for PortRef Rewriting the type checking around PortRef, which was interacting strangely with other Python scripts. Tested-by: stephan.diestelhorst@arm.com |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | Switch.cc | 11422:4f749e00b667 Tue Nov 18 09:00:00 EST 2014 Akash Bagdia <akash.bagdia@ARM.com> power: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. 10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54 The changeset ad9c042dce54 made changes to the structures under the network directory to use a map of buffers instead of vector of buffers. The reasoning was that not all vnets that are created are used and we needlessly allocate more buffers than required and then iterate over them while processing network messages. But the move to map resulted in a slow down which was pointed out by Andreas Hansson. This patch moves things back to using vector of message buffers. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. 10076:f81d94b53661 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: removes unused code. |
H A D | PerfectSwitch.cc | 10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54 The changeset ad9c042dce54 made changes to the structures under the network directory to use a map of buffers instead of vector of buffers. The reasoning was that not all vnets that are created are used and we needlessly allocate more buffers than required and then iterate over them while processing network messages. But the move to map resulted in a slow down which was pointed out by Andreas Hansson. This patch moves things back to using vector of message buffers. 10348:c91b23c72d5e Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> base: Use the global Mersenne twister throughout This patch tidies up random number generation to ensure that it is done consistently throughout the code base. In essence this involves a clean-up of Ruby, and some code simplifications in the traffic generator. As part of this patch a bunch of skewed distributions (off-by-one etc) have been fixed. Note that a single global random number generator is used, and that the object instantiation order will impact the behaviour (the sequence of numbers will be unaffected, but if module A calles random before module B then they would obviously see a different outcome). The dependency on the instantiation order is true in any case due to the execution-model of gem5, so we leave it as is. Also note that the global ranom generator is not thread safe at this point. Regressions using the memtest, TrafficGen or any Ruby tester are affected and will be updated accordingly. 10312:08f4deeb5b48 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: PerfectSwitch: moves code to a per vnet helper function This patch moves code from the wakeup() function to a operateVnet(). The aim is to improve the readiblity of the code. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. 10226:056363356d15 Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: drop dequeue_getDelayCycles() The functionality of updating and returning the delay cycles would now be performed by the dequeue() function itself. 10074:0e013fa647ac Thu Feb 20 18:26:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: removes some unecessary functions. |
H A D | SimpleNetwork.cc | 11422:4f749e00b667 Tue Nov 18 09:00:00 EST 2014 Akash Bagdia <akash.bagdia@ARM.com> power: Add power states to ClockedObject Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats. 10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54 The changeset ad9c042dce54 made changes to the structures under the network directory to use a map of buffers instead of vector of buffers. The reasoning was that not all vnets that are created are used and we needlessly allocate more buffers than required and then iterate over them while processing network messages. But the move to map resulted in a slow down which was pointed out by Andreas Hansson. This patch moves things back to using vector of message buffers. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10303:71e0934af9f1 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move getNumNodes() to base class All the implementations were doing the same things. 10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. 10082:70f350b13ec0 Fri Feb 21 09:02:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move message buffers to base network class. 10076:f81d94b53661 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: removes unused code. |
/gem5/src/cpu/testers/rubytest/ | ||
H A D | Check.cc | 10566:c99c8d2a7c31 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Assume all dynamic packet data is array allocated This patch simplifies how we deal with dynamically allocated data in the packet, always assuming that it is array allocated, and hence should be array deallocated (delete[] as opposed to delete). The only uses of dataDynamic was in the Ruby testers. The ARRAY_DATA flag in the packet is removed accordingly. No defragmentation of the flags is done at this point, leaving a gap in the bit masks. As the last part the patch, it renames dataDynamicArray to dataDynamic. 10563:755b18321206 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add const getters for write packet data This patch takes a first step in tightening up how we use the data pointer in write packets. A const getter is added for the pointer itself (getConstPtr), and a number of member functions are also made const accordingly. In a range of places throughout the memory system the new member is used. The patch also removes the unused isReadWrite function. 10562:b99fdc295c34 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Remove null-check bypassing in Packet::getPtr This patch removes the parameter that enables bypassing the null check in the Packet::getPtr method. A number of call sites assume the value to be non-null. The one odd case is the RubyTester, which issues zero-sized prefetches(!), and despite being reads they had no valid data pointer. This is now fixed, but the size oddity remains (unless anyone object or has any good suggestions). Finally, in the Ruby Sequencer, appropriate checks are made for flush packets as they have no valid data pointer. 10348:c91b23c72d5e Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> base: Use the global Mersenne twister throughout This patch tidies up random number generation to ensure that it is done consistently throughout the code base. In essence this involves a clean-up of Ruby, and some code simplifications in the traffic generator. As part of this patch a bunch of skewed distributions (off-by-one etc) have been fixed. Note that a single global random number generator is used, and that the object instantiation order will impact the behaviour (the sequence of numbers will be unaffected, but if module A calles random before module B then they would obviously see a different outcome). The dependency on the instantiation order is true in any case due to the execution-model of gem5, so we leave it as is. Also note that the global ranom generator is not thread safe at this point. Regressions using the memtest, TrafficGen or any Ruby tester are affected and will be updated accordingly. 10302:0e9e99e6369a Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type Time There is another type Time in src/base class which results in a conflict. |
/gem5/configs/example/ | ||
H A D | ruby_mem_test.py | 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10405:7a618c07e663 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. 10120:f5ceb3c3edb6 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: rename _cpu_ruby_ports to _cpu_ports 10083:2beea2a439b4 Fri Feb 21 09:02:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby_random_test: updates due to recent unrelated changes |
H A D | ruby_random_test.py | 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10300:ed3816dae6d5 Mon Sep 01 17:55:00 EDT 2014 Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu> ruby: Fixes clock domains in configuration files This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu> 10120:f5ceb3c3edb6 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: rename _cpu_ruby_ports to _cpu_ports 10083:2beea2a439b4 Fri Feb 21 09:02:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby_random_test: updates due to recent unrelated changes |
/gem5/tests/configs/ | ||
H A D | simple-timing-ruby.py | 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10120:f5ceb3c3edb6 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: rename _cpu_ruby_ports to _cpu_ports 10117:37e333de580f Thu Mar 20 09:03:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: no piobus in se mode Piobus was recently added to se scripts for ruby so that the interrupt controller can be connected to something (required since the interrupt controller sends address range messages). This patch removes the piobus and instead, the pio port of ruby port will now ignore the range change messages in se mode. 10092:c0db268f811b Mon Feb 24 21:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: correct errors in changeset 4eec7bdde5b0 Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols. |
/gem5/src/mem/ruby/system/ | ||
H A D | Sequencer.py | 10525:77787650cbbc Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: provide a backing store Ruby's functional accesses are not guaranteed to succeed as of now. While this is not a problem for the protocols that are currently in the mainline repo, it seems that coherence protocols for gpus rely on a backing store to supply the correct data. The aim of this patch is to make this backing store configurable i.e. it comes into play only when a particular option: --access-backing-store is invoked. The backing store has been there since M5 and GEMS were integrated. The only difference is that earlier the system used to maintain the backing store and ruby's copy was write-only. Sometime last year, we moved to data being supplied supplied by ruby in SE mode simulations. And now we have patches on the reviewboard, which remove ruby's copy of memory altogether and rely completely on the system's memory to supply data. This patch adds back a SimpleMemory member to RubySystem. This member is used only if the option: access-backing-store is set to true. By default, the memory would not be accessed. 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. 10518:30e3715c9405 Thu Nov 06 01:55:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: dma sequencer: remove RubyPort as parent class As of now DMASequencer inherits from the RubyPort class. But the code in RubyPort class is heavily tailored for the CPU Sequencer. There are parts of the code that are not required at all for the DMA sequencer. Moreover, the next patch uses the dma sequencer for carrying out memory accesses for all the io devices. Hence, it is better to have a leaner dma sequencer. 10090:4eec7bdde5b0 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: route all packets through ruby port Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch. |
/gem5/src/mem/slicc/ | ||
H A D | parser.py | 10308:8c0870dbae5c Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: change the way configurable members are specified There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='. 10307:6df951dcd7d9 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: improve the grammar This patch changes the grammar for SLICC so as to remove some of the redundant / duplicate rules. In particular rules for object/variable declaration and class member declaration have been unified. Similarly, the rules for a general function and a class method have been unified. One more change is in the priority of two rules. The first rule is on declaring a function with all the params typed and named. The second rule is on declaring a function with all the params only typed. Earlier the second rule had a higher priority. Now the first rule has a higher priority. 10165:7e9edf4297a9 Sat Apr 19 10:00:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: slight change to rule for transitions It had an unnecessary pairs token which is being removed. 10155:3b0bcc8c34ca Tue Apr 08 14:26:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: change enqueue statement As of now, the enqueue statement can take in any number of 'pairs' as argument. But we only use the pair in which latency is the key. This latency is allowed to be either a fixed integer or a member variable of controller in which the expression appears. This patch drops the use of pairs in an enqueue statement. Instead, an expression is allowed which will be interpreted to be the latency of the enqueue. This expression can anything allowed by slicc including a constant integer or a member variable. 10085:b9891fbae4c8 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove unused COPY_HEAD functionality |
/gem5/src/mem/ruby/network/ | ||
H A D | Network.hh | 10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54 The changeset ad9c042dce54 made changes to the structures under the network directory to use a map of buffers instead of vector of buffers. The reasoning was that not all vnets that are created are used and we needlessly allocate more buffers than required and then iterate over them while processing network messages. But the move to map resulted in a slow down which was pointed out by Andreas Hansson. This patch moves things back to using vector of message buffers. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10303:71e0934af9f1 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move getNumNodes() to base class All the implementations were doing the same things. 10082:70f350b13ec0 Fri Feb 21 09:02:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move message buffers to base network class. 10076:f81d94b53661 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: removes unused code. |
/gem5/src/mem/slicc/symbols/ | ||
H A D | StateMachine.py | 10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. 10523:5777a3e55603 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the function functionalReadBuffers() This function was added when I had incorrectly arrived at the conclusion that such a function can improve the chances of a functional read succeeding. As was later realized, this is not possible in the current setup. While the code using this function was dropped long back, this function was not. Hence the patch. 10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. 10308:8c0870dbae5c Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: change the way configurable members are specified There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='. 10307:6df951dcd7d9 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: improve the grammar This patch changes the grammar for SLICC so as to remove some of the redundant / duplicate rules. In particular rules for object/variable declaration and class member declaration have been unified. Similarly, the rules for a general function and a class method have been unified. One more change is in the priority of two rules. The first rule is on declaring a function with all the params typed and named. The second rule is on declaring a function with all the params only typed. Earlier the second rule had a higher priority. Now the first rule has a higher priority. 10305:76745b567dc3 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: donot prefix machine name to variables This changeset does away with prefixing of member variables of state machines with the identity of the machine itself. 10304:a2f88c6d9e54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove unused toString() from AbstractController 10228:1a85c4fc805c Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: remove unused ids DNUCA* 10121:64545628f5a7 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: slicc: code refactor 10078:9400a90ec5d1 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: controller: slight code refactoring |
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