110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 312856Sgiacomo.gabrielli@arm.com// Copyright (c) 2011-2014, 2017 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Gabe Black 3910037SARM gem5 Developers 4010037SARM gem5 Developerslet {{ 4110037SARM gem5 Developers 4210037SARM gem5 Developers header_output = "" 4310037SARM gem5 Developers decoder_output = "" 4410037SARM gem5 Developers exec_output = "" 4510037SARM gem5 Developers 4610037SARM gem5 Developers class LoadInst64(LoadStoreInst): 4710037SARM gem5 Developers execBase = 'Load64' 4810037SARM gem5 Developers micro = False 4910037SARM gem5 Developers 5010037SARM gem5 Developers def __init__(self, mnem, Name, size=4, sign=False, user=False, 5110037SARM gem5 Developers literal=False, flavor="normal", top=False): 5210037SARM gem5 Developers super(LoadInst64, self).__init__() 5310037SARM gem5 Developers 5410037SARM gem5 Developers self.name = mnem 5510037SARM gem5 Developers self.Name = Name 5610037SARM gem5 Developers self.size = size 5710037SARM gem5 Developers self.sign = sign 5810037SARM gem5 Developers self.user = user 5910037SARM gem5 Developers self.literal = literal 6010037SARM gem5 Developers self.flavor = flavor 6110037SARM gem5 Developers self.top = top 6210037SARM gem5 Developers 6310037SARM gem5 Developers self.memFlags = ["ArmISA::TLB::MustBeOne"] 6410037SARM gem5 Developers self.instFlags = [] 6510037SARM gem5 Developers self.codeBlobs = {"postacc_code" : ""} 6610037SARM gem5 Developers 6710037SARM gem5 Developers # Add memory request flags where necessary 6810037SARM gem5 Developers if self.user: 6910037SARM gem5 Developers self.memFlags.append("ArmISA::TLB::UserMode") 7010037SARM gem5 Developers 7110037SARM gem5 Developers if self.flavor == "dprefetch": 7210037SARM gem5 Developers self.memFlags.append("Request::PREFETCH") 7310037SARM gem5 Developers self.instFlags = ['IsDataPrefetch'] 7410037SARM gem5 Developers elif self.flavor == "iprefetch": 7510037SARM gem5 Developers self.memFlags.append("Request::PREFETCH") 7610037SARM gem5 Developers self.instFlags = ['IsInstPrefetch'] 7713367Syuetsu.kodama@riken.jp elif self.flavor == "mprefetch": 7813367Syuetsu.kodama@riken.jp self.memFlags.append("((((dest>>3)&3)==2)? \ 7913367Syuetsu.kodama@riken.jp (Request::PF_EXCLUSIVE):(Request::PREFETCH))") 8013367Syuetsu.kodama@riken.jp self.instFlags = ['IsDataPrefetch'] 8110037SARM gem5 Developers if self.micro: 8210037SARM gem5 Developers self.instFlags.append("IsMicroop") 8310037SARM gem5 Developers 8410037SARM gem5 Developers if self.flavor in ("acexp", "exp"): 8510037SARM gem5 Developers # For exclusive pair ops alignment check is based on total size 8610037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2) + 1)) 8710037SARM gem5 Developers elif not (self.size == 16 and self.top): 8810037SARM gem5 Developers # Only the first microop should perform alignment checking. 8910037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2))) 9010037SARM gem5 Developers 9110037SARM gem5 Developers if self.flavor not in ("acquire", "acex", "exclusive", 9210037SARM gem5 Developers "acexp", "exp"): 9310037SARM gem5 Developers self.memFlags.append("ArmISA::TLB::AllowUnaligned") 9410037SARM gem5 Developers 9510037SARM gem5 Developers if self.flavor in ("acquire", "acex", "acexp"): 9610037SARM gem5 Developers self.instFlags.extend(["IsMemBarrier", 9710037SARM gem5 Developers "IsWriteBarrier", 9810037SARM gem5 Developers "IsReadBarrier"]) 9910037SARM gem5 Developers if self.flavor in ("acex", "exclusive", "exp", "acexp"): 10010037SARM gem5 Developers self.memFlags.append("Request::LLSC") 10110037SARM gem5 Developers 10214058Sgiacomo.travaglini@arm.com # Using a different execute template for fp flavoured loads. 10314058Sgiacomo.travaglini@arm.com # In this specific template the memacc_code is executed 10414058Sgiacomo.travaglini@arm.com # conditionally depending of wether the memory load has 10514058Sgiacomo.travaglini@arm.com # generated any fault 10614058Sgiacomo.travaglini@arm.com if flavor == "fp": 10714058Sgiacomo.travaglini@arm.com self.fullExecTemplate = eval(self.execBase + 'FpExecute') 10814058Sgiacomo.travaglini@arm.com 10910037SARM gem5 Developers def buildEACode(self): 11010037SARM gem5 Developers # Address computation code 11110037SARM gem5 Developers eaCode = "" 11210037SARM gem5 Developers if self.flavor == "fp": 11310037SARM gem5 Developers eaCode += vfp64EnabledCheckCode 11410037SARM gem5 Developers 11510037SARM gem5 Developers if self.literal: 11610037SARM gem5 Developers eaCode += "EA = RawPC" 11710037SARM gem5 Developers else: 11810037SARM gem5 Developers eaCode += SPAlignmentCheckCode + "EA = XBase" 11910037SARM gem5 Developers 12010037SARM gem5 Developers if self.size == 16: 12110037SARM gem5 Developers if self.top: 12210037SARM gem5 Developers eaCode += " + (isBigEndian64(xc->tcBase()) ? 0 : 8)" 12310037SARM gem5 Developers else: 12410037SARM gem5 Developers eaCode += " + (isBigEndian64(xc->tcBase()) ? 8 : 0)" 12510037SARM gem5 Developers if not self.post: 12610037SARM gem5 Developers eaCode += self.offset 12710037SARM gem5 Developers eaCode += ";" 12810037SARM gem5 Developers 12910037SARM gem5 Developers self.codeBlobs["ea_code"] = eaCode 13010037SARM gem5 Developers 13110037SARM gem5 Developers def emitHelper(self, base='Memory64', wbDecl=None): 13210037SARM gem5 Developers global header_output, decoder_output, exec_output 13310037SARM gem5 Developers 13410037SARM gem5 Developers # If this is a microop itself, don't allow anything that would 13510037SARM gem5 Developers # require further microcoding. 13610037SARM gem5 Developers if self.micro: 13710037SARM gem5 Developers assert not wbDecl 13810037SARM gem5 Developers 13910037SARM gem5 Developers fa_code = None 14010037SARM gem5 Developers if not self.micro and self.flavor in ("normal", "widen", "acquire"): 14110037SARM gem5 Developers fa_code = ''' 14210037SARM gem5 Developers fault->annotate(ArmFault::SAS, %s); 14310037SARM gem5 Developers fault->annotate(ArmFault::SSE, %s); 14410037SARM gem5 Developers fault->annotate(ArmFault::SRT, dest); 14510037SARM gem5 Developers fault->annotate(ArmFault::SF, %s); 14610037SARM gem5 Developers fault->annotate(ArmFault::AR, %s); 14710037SARM gem5 Developers ''' % ("0" if self.size == 1 else 14810037SARM gem5 Developers "1" if self.size == 2 else 14910037SARM gem5 Developers "2" if self.size == 4 else "3", 15010037SARM gem5 Developers "true" if self.sign else "false", 15110037SARM gem5 Developers "true" if (self.size == 8 or 15210037SARM gem5 Developers self.flavor == "widen") else "false", 15310037SARM gem5 Developers "true" if self.flavor == "acquire" else "false") 15410037SARM gem5 Developers 15510037SARM gem5 Developers (newHeader, newDecoder, newExec) = \ 15610037SARM gem5 Developers self.fillTemplates(self.name, self.Name, self.codeBlobs, 15710037SARM gem5 Developers self.memFlags, self.instFlags, 15810037SARM gem5 Developers base, wbDecl, faCode=fa_code) 15910037SARM gem5 Developers 16010037SARM gem5 Developers header_output += newHeader 16110037SARM gem5 Developers decoder_output += newDecoder 16210037SARM gem5 Developers exec_output += newExec 16310037SARM gem5 Developers 16410037SARM gem5 Developers class LoadImmInst64(LoadInst64): 16510037SARM gem5 Developers def __init__(self, *args, **kargs): 16610037SARM gem5 Developers super(LoadImmInst64, self).__init__(*args, **kargs) 16710037SARM gem5 Developers self.offset = " + imm" 16810037SARM gem5 Developers 16910037SARM gem5 Developers self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);" 17010037SARM gem5 Developers 17110037SARM gem5 Developers class LoadRegInst64(LoadInst64): 17210037SARM gem5 Developers def __init__(self, *args, **kargs): 17310037SARM gem5 Developers super(LoadRegInst64, self).__init__(*args, **kargs) 17410037SARM gem5 Developers self.offset = " + extendReg64(XOffset, type, shiftAmt, 64)" 17510037SARM gem5 Developers 17610037SARM gem5 Developers self.wbDecl = \ 17710037SARM gem5 Developers "MicroAddXERegUop(machInst, base, base, " + \ 17810037SARM gem5 Developers " offset, type, shiftAmt);" 17910037SARM gem5 Developers 18010037SARM gem5 Developers class LoadRawRegInst64(LoadInst64): 18110037SARM gem5 Developers def __init__(self, *args, **kargs): 18210037SARM gem5 Developers super(LoadRawRegInst64, self).__init__(*args, **kargs) 18310037SARM gem5 Developers self.offset = "" 18410037SARM gem5 Developers 18510037SARM gem5 Developers class LoadSingle64(LoadInst64): 18610037SARM gem5 Developers def emit(self): 18710037SARM gem5 Developers self.buildEACode() 18810037SARM gem5 Developers 18913759Sgiacomo.gabrielli@arm.com accEpilogCode = None 19010037SARM gem5 Developers # Code that actually handles the access 19113367Syuetsu.kodama@riken.jp if self.flavor in ("dprefetch", "iprefetch", "mprefetch"): 19210037SARM gem5 Developers accCode = 'uint64_t temp M5_VAR_USED = Mem%s;' 19310037SARM gem5 Developers elif self.flavor == "fp": 19413759Sgiacomo.gabrielli@arm.com accEpilogCode = ''' 19513915Sgabeblack@google.com ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest, 19613759Sgiacomo.gabrielli@arm.com ArmStaticInst::getCurSveVecLen<uint64_t>( 19713759Sgiacomo.gabrielli@arm.com xc->tcBase())); 19813759Sgiacomo.gabrielli@arm.com ''' 19910037SARM gem5 Developers if self.size in (1, 2, 4): 20010037SARM gem5 Developers accCode = ''' 20110037SARM gem5 Developers AA64FpDestP0_uw = cSwap(Mem%s, 20210037SARM gem5 Developers isBigEndian64(xc->tcBase())); 20310037SARM gem5 Developers AA64FpDestP1_uw = 0; 20410037SARM gem5 Developers AA64FpDestP2_uw = 0; 20510037SARM gem5 Developers AA64FpDestP3_uw = 0; 20610037SARM gem5 Developers ''' 20710346Smitch.hayenga@arm.com elif self.size == 8: 20810037SARM gem5 Developers accCode = ''' 20910037SARM gem5 Developers uint64_t data = cSwap(Mem%s, 21010037SARM gem5 Developers isBigEndian64(xc->tcBase())); 21110037SARM gem5 Developers AA64FpDestP0_uw = (uint32_t)data; 21210037SARM gem5 Developers AA64FpDestP1_uw = (data >> 32); 21310346Smitch.hayenga@arm.com AA64FpDestP2_uw = 0; 21410346Smitch.hayenga@arm.com AA64FpDestP3_uw = 0; 21510037SARM gem5 Developers ''' 21610346Smitch.hayenga@arm.com elif self.size == 16: 21710037SARM gem5 Developers accCode = ''' 21812386Sgabeblack@google.com auto data = cSwap(Mem%s, isBigEndian64(xc->tcBase())); 21912386Sgabeblack@google.com AA64FpDestP0_uw = (uint32_t)data[0]; 22012386Sgabeblack@google.com AA64FpDestP1_uw = (data[0] >> 32); 22112386Sgabeblack@google.com AA64FpDestP2_uw = (uint32_t)data[1]; 22212386Sgabeblack@google.com AA64FpDestP3_uw = (data[1] >> 32); 22310037SARM gem5 Developers ''' 22410037SARM gem5 Developers elif self.flavor == "widen" or self.size == 8: 22510037SARM gem5 Developers accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));" 22610037SARM gem5 Developers else: 22710037SARM gem5 Developers accCode = "WDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));" 22810346Smitch.hayenga@arm.com 22910346Smitch.hayenga@arm.com accCode = accCode % buildMemSuffix(self.sign, self.size) 23010037SARM gem5 Developers 23110037SARM gem5 Developers self.codeBlobs["memacc_code"] = accCode 23213759Sgiacomo.gabrielli@arm.com if accEpilogCode: 23313759Sgiacomo.gabrielli@arm.com self.codeBlobs["memacc_epilog_code"] = accEpilogCode 23410037SARM gem5 Developers 23510037SARM gem5 Developers # Push it out to the output files 23610037SARM gem5 Developers wbDecl = None 23710037SARM gem5 Developers if self.writeback and not self.micro: 23810037SARM gem5 Developers wbDecl = self.wbDecl 23910037SARM gem5 Developers self.emitHelper(self.base, wbDecl) 24010037SARM gem5 Developers 24110037SARM gem5 Developers class LoadDouble64(LoadInst64): 24210037SARM gem5 Developers def emit(self): 24310037SARM gem5 Developers self.buildEACode() 24410037SARM gem5 Developers 24513759Sgiacomo.gabrielli@arm.com accEpilogCode = None 24610037SARM gem5 Developers # Code that actually handles the access 24710037SARM gem5 Developers if self.flavor == "fp": 24813759Sgiacomo.gabrielli@arm.com accEpilogCode = ''' 24913915Sgabeblack@google.com ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest, 25013759Sgiacomo.gabrielli@arm.com ArmStaticInst::getCurSveVecLen<uint64_t>( 25113759Sgiacomo.gabrielli@arm.com xc->tcBase())); 25213915Sgabeblack@google.com ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2, 25313759Sgiacomo.gabrielli@arm.com ArmStaticInst::getCurSveVecLen<uint64_t>( 25413759Sgiacomo.gabrielli@arm.com xc->tcBase())); 25513759Sgiacomo.gabrielli@arm.com ''' 25610346Smitch.hayenga@arm.com if self.size == 4: 25710346Smitch.hayenga@arm.com accCode = ''' 25810346Smitch.hayenga@arm.com uint64_t data = cSwap(Mem_ud, isBigEndian64(xc->tcBase())); 25912527Schuan.zhu@arm.com AA64FpDestP0_uw = isBigEndian64(xc->tcBase()) 26012527Schuan.zhu@arm.com ? (data >> 32) 26112527Schuan.zhu@arm.com : (uint32_t)data; 26210346Smitch.hayenga@arm.com AA64FpDestP1_uw = 0; 26310346Smitch.hayenga@arm.com AA64FpDestP2_uw = 0; 26410346Smitch.hayenga@arm.com AA64FpDestP3_uw = 0; 26512527Schuan.zhu@arm.com AA64FpDest2P0_uw = isBigEndian64(xc->tcBase()) 26612527Schuan.zhu@arm.com ? (uint32_t)data 26712527Schuan.zhu@arm.com : (data >> 32); 26810346Smitch.hayenga@arm.com AA64FpDest2P1_uw = 0; 26910346Smitch.hayenga@arm.com AA64FpDest2P2_uw = 0; 27010346Smitch.hayenga@arm.com AA64FpDest2P3_uw = 0; 27110346Smitch.hayenga@arm.com ''' 27210346Smitch.hayenga@arm.com elif self.size == 8: 27310346Smitch.hayenga@arm.com accCode = ''' 27412527Schuan.zhu@arm.com uint64_t data_a = cSwap(Mem_tud[0], 27512527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 27612527Schuan.zhu@arm.com uint64_t data_b = cSwap(Mem_tud[1], 27712527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 27812527Schuan.zhu@arm.com AA64FpDestP0_uw = (uint32_t)data_a; 27912527Schuan.zhu@arm.com AA64FpDestP1_uw = (uint32_t)(data_a >> 32); 28010346Smitch.hayenga@arm.com AA64FpDestP2_uw = 0; 28110346Smitch.hayenga@arm.com AA64FpDestP3_uw = 0; 28212527Schuan.zhu@arm.com AA64FpDest2P0_uw = (uint32_t)data_b; 28312527Schuan.zhu@arm.com AA64FpDest2P1_uw = (uint32_t)(data_b >> 32); 28410346Smitch.hayenga@arm.com AA64FpDest2P2_uw = 0; 28510346Smitch.hayenga@arm.com AA64FpDest2P3_uw = 0; 28610346Smitch.hayenga@arm.com ''' 28710037SARM gem5 Developers else: 28810037SARM gem5 Developers if self.sign: 28910037SARM gem5 Developers if self.size == 4: 29010037SARM gem5 Developers accCode = ''' 29110037SARM gem5 Developers uint64_t data = cSwap(Mem_ud, 29210037SARM gem5 Developers isBigEndian64(xc->tcBase())); 29312527Schuan.zhu@arm.com XDest = isBigEndian64(xc->tcBase()) 29412527Schuan.zhu@arm.com ? sext<32>(data >> 32) 29512527Schuan.zhu@arm.com : sext<32>((uint32_t)data); 29612527Schuan.zhu@arm.com XDest2 = isBigEndian64(xc->tcBase()) 29712527Schuan.zhu@arm.com ? sext<32>((uint32_t)data) 29812527Schuan.zhu@arm.com : sext<32>(data >> 32); 29910037SARM gem5 Developers ''' 30010037SARM gem5 Developers elif self.size == 8: 30110037SARM gem5 Developers accCode = ''' 30212527Schuan.zhu@arm.com XDest = cSwap(Mem_tud[0], 30312527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 30412527Schuan.zhu@arm.com XDest2 = cSwap(Mem_tud[1], 30512527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 30610037SARM gem5 Developers ''' 30710037SARM gem5 Developers else: 30810037SARM gem5 Developers if self.size == 4: 30910037SARM gem5 Developers accCode = ''' 31010037SARM gem5 Developers uint64_t data = cSwap(Mem_ud, 31110037SARM gem5 Developers isBigEndian64(xc->tcBase())); 31212527Schuan.zhu@arm.com XDest = isBigEndian64(xc->tcBase()) 31312527Schuan.zhu@arm.com ? (data >> 32) 31412527Schuan.zhu@arm.com : (uint32_t)data; 31512527Schuan.zhu@arm.com XDest2 = isBigEndian64(xc->tcBase()) 31612527Schuan.zhu@arm.com ? (uint32_t)data 31712527Schuan.zhu@arm.com : (data >> 32); 31810037SARM gem5 Developers ''' 31910037SARM gem5 Developers elif self.size == 8: 32010037SARM gem5 Developers accCode = ''' 32112527Schuan.zhu@arm.com XDest = cSwap(Mem_tud[0], 32212527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 32312527Schuan.zhu@arm.com XDest2 = cSwap(Mem_tud[1], 32412527Schuan.zhu@arm.com isBigEndian64(xc->tcBase())); 32510037SARM gem5 Developers ''' 32610037SARM gem5 Developers self.codeBlobs["memacc_code"] = accCode 32713759Sgiacomo.gabrielli@arm.com if accEpilogCode: 32813759Sgiacomo.gabrielli@arm.com self.codeBlobs["memacc_epilog_code"] = accEpilogCode 32910037SARM gem5 Developers 33010037SARM gem5 Developers # Push it out to the output files 33110037SARM gem5 Developers wbDecl = None 33210037SARM gem5 Developers if self.writeback and not self.micro: 33310037SARM gem5 Developers wbDecl = self.wbDecl 33410037SARM gem5 Developers self.emitHelper(self.base, wbDecl) 33510037SARM gem5 Developers 33610037SARM gem5 Developers class LoadImm64(LoadImmInst64, LoadSingle64): 33710037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 33810037SARM gem5 Developers base = 'ArmISA::MemoryImm64' 33910037SARM gem5 Developers writeback = False 34010037SARM gem5 Developers post = False 34110037SARM gem5 Developers 34210037SARM gem5 Developers class LoadPre64(LoadImmInst64, LoadSingle64): 34310037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 34410037SARM gem5 Developers base = 'ArmISA::MemoryPreIndex64' 34510037SARM gem5 Developers writeback = True 34610037SARM gem5 Developers post = False 34710037SARM gem5 Developers 34810037SARM gem5 Developers class LoadPost64(LoadImmInst64, LoadSingle64): 34910037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 35010037SARM gem5 Developers base = 'ArmISA::MemoryPostIndex64' 35110037SARM gem5 Developers writeback = True 35210037SARM gem5 Developers post = True 35310037SARM gem5 Developers 35410037SARM gem5 Developers class LoadReg64(LoadRegInst64, LoadSingle64): 35510037SARM gem5 Developers decConstBase = 'LoadStoreReg64' 35610037SARM gem5 Developers base = 'ArmISA::MemoryReg64' 35710037SARM gem5 Developers writeback = False 35810037SARM gem5 Developers post = False 35910037SARM gem5 Developers 36010037SARM gem5 Developers class LoadRaw64(LoadRawRegInst64, LoadSingle64): 36110037SARM gem5 Developers decConstBase = 'LoadStoreRaw64' 36210037SARM gem5 Developers base = 'ArmISA::MemoryRaw64' 36310037SARM gem5 Developers writeback = False 36410037SARM gem5 Developers post = False 36510037SARM gem5 Developers 36610037SARM gem5 Developers class LoadEx64(LoadRawRegInst64, LoadSingle64): 36710037SARM gem5 Developers decConstBase = 'LoadStoreEx64' 36810037SARM gem5 Developers base = 'ArmISA::MemoryEx64' 36910037SARM gem5 Developers writeback = False 37010037SARM gem5 Developers post = False 37110037SARM gem5 Developers 37210037SARM gem5 Developers class LoadLit64(LoadImmInst64, LoadSingle64): 37310037SARM gem5 Developers decConstBase = 'LoadStoreLit64' 37410037SARM gem5 Developers base = 'ArmISA::MemoryLiteral64' 37510037SARM gem5 Developers writeback = False 37610037SARM gem5 Developers post = False 37710037SARM gem5 Developers 37810037SARM gem5 Developers def buildLoads64(mnem, NameBase, size, sign, flavor="normal"): 37910037SARM gem5 Developers LoadImm64(mnem, NameBase + "_IMM", size, sign, flavor=flavor).emit() 38010037SARM gem5 Developers LoadPre64(mnem, NameBase + "_PRE", size, sign, flavor=flavor).emit() 38110037SARM gem5 Developers LoadPost64(mnem, NameBase + "_POST", size, sign, flavor=flavor).emit() 38210037SARM gem5 Developers LoadReg64(mnem, NameBase + "_REG", size, sign, flavor=flavor).emit() 38310037SARM gem5 Developers 38410037SARM gem5 Developers buildLoads64("ldrb", "LDRB64", 1, False) 38510037SARM gem5 Developers buildLoads64("ldrsb", "LDRSBW64", 1, True) 38610037SARM gem5 Developers buildLoads64("ldrsb", "LDRSBX64", 1, True, flavor="widen") 38710037SARM gem5 Developers buildLoads64("ldrh", "LDRH64", 2, False) 38810037SARM gem5 Developers buildLoads64("ldrsh", "LDRSHW64", 2, True) 38910037SARM gem5 Developers buildLoads64("ldrsh", "LDRSHX64", 2, True, flavor="widen") 39010037SARM gem5 Developers buildLoads64("ldrsw", "LDRSW64", 4, True, flavor="widen") 39110037SARM gem5 Developers buildLoads64("ldr", "LDRW64", 4, False) 39210037SARM gem5 Developers buildLoads64("ldr", "LDRX64", 8, False) 39310037SARM gem5 Developers buildLoads64("ldr", "LDRBFP64", 1, False, flavor="fp") 39410037SARM gem5 Developers buildLoads64("ldr", "LDRHFP64", 2, False, flavor="fp") 39510037SARM gem5 Developers buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp") 39610037SARM gem5 Developers buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp") 39710037SARM gem5 Developers 39813367Syuetsu.kodama@riken.jp LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit() 39913367Syuetsu.kodama@riken.jp LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit() 40013367Syuetsu.kodama@riken.jp LoadLit64("prfm", "PRFM64_LIT", 8, literal=True, 40113367Syuetsu.kodama@riken.jp flavor="mprefetch").emit() 40213367Syuetsu.kodama@riken.jp LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit() 40310037SARM gem5 Developers 40410037SARM gem5 Developers LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit() 40510037SARM gem5 Developers LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit() 40610037SARM gem5 Developers LoadImm64("ldursb", "LDURSBX64_IMM", 1, True, flavor="widen").emit() 40710037SARM gem5 Developers LoadImm64("ldurh", "LDURH64_IMM", 2, False).emit() 40810037SARM gem5 Developers LoadImm64("ldursh", "LDURSHW64_IMM", 2, True).emit() 40910037SARM gem5 Developers LoadImm64("ldursh", "LDURSHX64_IMM", 2, True, flavor="widen").emit() 41010037SARM gem5 Developers LoadImm64("ldursw", "LDURSW64_IMM", 4, True, flavor="widen").emit() 41110037SARM gem5 Developers LoadImm64("ldur", "LDURW64_IMM", 4, False).emit() 41210037SARM gem5 Developers LoadImm64("ldur", "LDURX64_IMM", 8, False).emit() 41310037SARM gem5 Developers LoadImm64("ldur", "LDURBFP64_IMM", 1, flavor="fp").emit() 41410037SARM gem5 Developers LoadImm64("ldur", "LDURHFP64_IMM", 2, flavor="fp").emit() 41510037SARM gem5 Developers LoadImm64("ldur", "LDURSFP64_IMM", 4, flavor="fp").emit() 41610037SARM gem5 Developers LoadImm64("ldur", "LDURDFP64_IMM", 8, flavor="fp").emit() 41710037SARM gem5 Developers 41810037SARM gem5 Developers LoadImm64("ldtrb", "LDTRB64_IMM", 1, False, True).emit() 41910037SARM gem5 Developers LoadImm64("ldtrsb", "LDTRSBW64_IMM", 1, True, True).emit() 42010037SARM gem5 Developers LoadImm64("ldtrsb", "LDTRSBX64_IMM", 1, True, True, flavor="widen").emit() 42110037SARM gem5 Developers LoadImm64("ldtrh", "LDTRH64_IMM", 2, False, True).emit() 42210037SARM gem5 Developers LoadImm64("ldtrsh", "LDTRSHW64_IMM", 2, True, True).emit() 42310037SARM gem5 Developers LoadImm64("ldtrsh", "LDTRSHX64_IMM", 2, True, True, flavor="widen").emit() 42410037SARM gem5 Developers LoadImm64("ldtrsw", "LDTRSW64_IMM", 4, True, flavor="widen").emit() 42510037SARM gem5 Developers LoadImm64("ldtr", "LDTRW64_IMM", 4, False, True).emit() 42610037SARM gem5 Developers LoadImm64("ldtr", "LDTRX64_IMM", 8, False, True).emit() 42710037SARM gem5 Developers 42810037SARM gem5 Developers LoadLit64("ldrsw", "LDRSWL64_LIT", 4, True, \ 42910037SARM gem5 Developers literal=True, flavor="widen").emit() 43010037SARM gem5 Developers LoadLit64("ldr", "LDRWL64_LIT", 4, False, literal=True).emit() 43110037SARM gem5 Developers LoadLit64("ldr", "LDRXL64_LIT", 8, False, literal=True).emit() 43210037SARM gem5 Developers LoadLit64("ldr", "LDRSFP64_LIT", 4, literal=True, flavor="fp").emit() 43310037SARM gem5 Developers LoadLit64("ldr", "LDRDFP64_LIT", 8, literal=True, flavor="fp").emit() 43410037SARM gem5 Developers 43510037SARM gem5 Developers LoadRaw64("ldar", "LDARX64", 8, flavor="acquire").emit() 43610037SARM gem5 Developers LoadRaw64("ldar", "LDARW64", 4, flavor="acquire").emit() 43710037SARM gem5 Developers LoadRaw64("ldarh", "LDARH64", 2, flavor="acquire").emit() 43810037SARM gem5 Developers LoadRaw64("ldarb", "LDARB64", 1, flavor="acquire").emit() 43910037SARM gem5 Developers 44010037SARM gem5 Developers LoadEx64("ldaxr", "LDAXRX64", 8, flavor="acex").emit() 44110037SARM gem5 Developers LoadEx64("ldaxr", "LDAXRW64", 4, flavor="acex").emit() 44210037SARM gem5 Developers LoadEx64("ldaxrh", "LDAXRH64", 2, flavor="acex").emit() 44310037SARM gem5 Developers LoadEx64("ldaxrb", "LDAXRB64", 1, flavor="acex").emit() 44410037SARM gem5 Developers 44510037SARM gem5 Developers LoadEx64("ldxr", "LDXRX64", 8, flavor="exclusive").emit() 44610037SARM gem5 Developers LoadEx64("ldxr", "LDXRW64", 4, flavor="exclusive").emit() 44710037SARM gem5 Developers LoadEx64("ldxrh", "LDXRH64", 2, flavor="exclusive").emit() 44810037SARM gem5 Developers LoadEx64("ldxrb", "LDXRB64", 1, flavor="exclusive").emit() 44910037SARM gem5 Developers 45012856Sgiacomo.gabrielli@arm.com LoadRaw64("ldapr", "LDAPRX64", 8, flavor="acquire").emit() 45112856Sgiacomo.gabrielli@arm.com LoadRaw64("ldapr", "LDAPRW64", 4, flavor="acquire").emit() 45212856Sgiacomo.gabrielli@arm.com LoadRaw64("ldaprh", "LDAPRH64", 2, flavor="acquire").emit() 45312856Sgiacomo.gabrielli@arm.com LoadRaw64("ldaprb", "LDAPRB64", 1, flavor="acquire").emit() 45412856Sgiacomo.gabrielli@arm.com 45510037SARM gem5 Developers class LoadImmU64(LoadImm64): 45610037SARM gem5 Developers decConstBase = 'LoadStoreImmU64' 45710037SARM gem5 Developers micro = True 45810037SARM gem5 Developers 45910037SARM gem5 Developers class LoadImmDU64(LoadImmInst64, LoadDouble64): 46010037SARM gem5 Developers decConstBase = 'LoadStoreImmDU64' 46110037SARM gem5 Developers base = 'ArmISA::MemoryDImm64' 46210037SARM gem5 Developers micro = True 46310037SARM gem5 Developers post = False 46410037SARM gem5 Developers writeback = False 46510037SARM gem5 Developers 46610037SARM gem5 Developers class LoadImmDouble64(LoadImmInst64, LoadDouble64): 46710037SARM gem5 Developers decConstBase = 'LoadStoreImmDU64' 46810037SARM gem5 Developers base = 'ArmISA::MemoryDImm64' 46910037SARM gem5 Developers micro = False 47010037SARM gem5 Developers post = False 47110037SARM gem5 Developers writeback = False 47210037SARM gem5 Developers 47310037SARM gem5 Developers class LoadRegU64(LoadReg64): 47410037SARM gem5 Developers decConstBase = 'LoadStoreRegU64' 47510037SARM gem5 Developers micro = True 47610037SARM gem5 Developers 47710037SARM gem5 Developers class LoadLitU64(LoadLit64): 47810037SARM gem5 Developers decConstBase = 'LoadStoreLitU64' 47910037SARM gem5 Developers micro = True 48010037SARM gem5 Developers 48110346Smitch.hayenga@arm.com LoadImmDU64("ldp_uop", "MicroLdPairUop", 8).emit() 48210346Smitch.hayenga@arm.com LoadImmDU64("ldp_fp8_uop", "MicroLdPairFp8Uop", 8, flavor="fp").emit() 48310346Smitch.hayenga@arm.com LoadImmU64("ldfp16_uop", "MicroLdFp16Uop", 16, flavor="fp").emit() 48410346Smitch.hayenga@arm.com LoadReg64("ldfp16reg_uop", "MicroLdFp16RegUop", 16, flavor="fp").emit() 48510346Smitch.hayenga@arm.com 48610037SARM gem5 Developers LoadImmDouble64("ldaxp", "LDAXPW64", 4, flavor="acexp").emit() 48710037SARM gem5 Developers LoadImmDouble64("ldaxp", "LDAXPX64", 8, flavor="acexp").emit() 48810037SARM gem5 Developers LoadImmDouble64("ldxp", "LDXPW64", 4, flavor="exp").emit() 48910037SARM gem5 Developers LoadImmDouble64("ldxp", "LDXPX64", 8, flavor="exp").emit() 49010037SARM gem5 Developers 49110037SARM gem5 Developers LoadImmU64("ldrxi_uop", "MicroLdrXImmUop", 8).emit() 49210037SARM gem5 Developers LoadRegU64("ldrxr_uop", "MicroLdrXRegUop", 8).emit() 49310037SARM gem5 Developers LoadLitU64("ldrxl_uop", "MicroLdrXLitUop", 8, literal=True).emit() 49410037SARM gem5 Developers LoadImmU64("ldrfpxi_uop", "MicroLdrFpXImmUop", 8, flavor="fp").emit() 49510037SARM gem5 Developers LoadRegU64("ldrfpxr_uop", "MicroLdrFpXRegUop", 8, flavor="fp").emit() 49610037SARM gem5 Developers LoadLitU64("ldrfpxl_uop", "MicroLdrFpXLitUop", 8, literal=True, 49710037SARM gem5 Developers flavor="fp").emit() 49810346Smitch.hayenga@arm.com LoadLitU64("ldfp16_lit__uop", "MicroLdFp16LitUop", 49910346Smitch.hayenga@arm.com 16, literal=True, flavor="fp").emit() 50010037SARM gem5 Developers LoadImmDU64("ldrduxi_uop", "MicroLdrDUXImmUop", 4, sign=False).emit() 50110037SARM gem5 Developers LoadImmDU64("ldrdsxi_uop", "MicroLdrDSXImmUop", 4, sign=True).emit() 50210037SARM gem5 Developers LoadImmDU64("ldrdfpxi_uop", "MicroLdrDFpXImmUop", 4, flavor="fp").emit() 50310037SARM gem5 Developers}}; 504