Searched hist:2011 (Results 326 - 350 of 897) sorted by relevance
/gem5/src/arch/x86/insts/ | ||
H A D | microldstop.cc | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/cpu/ | ||
H A D | intr_control.cc | 8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 8739:925f15f96322 Fri Sep 30 03:28:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the devices in SE mode. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
H A D | decode_cache.hh | 8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own. This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | SimpleNetwork.cc | 8645:89929730804b Sat Dec 31 19:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Shuffle some of the included files This patch adds and removes included files from some of the files so as to organize remove some false dependencies and include some files directly instead of transitively. 8530:3aaa99208a84 Mon Aug 29 06:10:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused code 8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use 8308:79cf09f5a234 Wed May 18 03:06:00 EDT 2011 Tushar Krishna <tushar@csail.mit.edu> slicc: added vnet_type field to identify response vnets from others Identifying response vnets versus other vnets will allow garnet to determine which vnets will carry data packets, and which will carry ctrl packets, and use appropriate buffer sizes (since data packets are larger than ctrl packets). This in turn allows the orion power model to accurately estimate buffer power. 8259:36987780169e Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: moved network config params Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of the top-level parent network object and to only those networks that actually use those parameters. 8258:7c377f5162f8 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: basic link bw for garnet and simple networks This patch ensures that both Garnet and the simple networks use the bw value specified in the topology. To do so, the patch generalizes the specification of bw for basic links. This value is then translated to the specific value used by the simple and Garnet networks. Since Garent does not support non-uniformed link bandwidth, the patch also adds a check to ensure all bws are equal. 8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. 8255:73089f793a0a Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: moved topology to the top network directory Moved the Topology class to the top network directory because it is shared by both the simple and Garnet networks. 7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace |
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/ | ||
H A D | call.py | 7872:b21a94bf6a28 Wed Feb 02 22:56:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Replace the stupd microop with a store/update sequence. |
/gem5/tests/configs/ | ||
H A D | realview-simple-timing.py | 8528:1f95c9a0bb2f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add some MP regressions and clean up the disk images and kernels a bit 8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. 8061:08e91664adac Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clarifies creation of Linux and baremetal ARM systems. makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems. 7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately. This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. |
/gem5/src/kern/ | ||
H A D | operatingsystem.hh | 8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. |
H A D | kernel_stats.cc | 8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS. 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/arch/power/ | ||
H A D | locked_mem.hh | 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/arch/sparc/ | ||
H A D | locked_mem.hh | 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/arch/alpha/ | ||
H A D | SConscript | 8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS. 8755:a9934545489d Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Alpha: Turn on vtophys in SE mode. 8745:575cab0db076 Sun Oct 09 03:15:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the Interrupt objects in SE mode. |
/gem5/src/mem/ruby/network/fault_model/ | ||
H A D | FaultModel.cc | 8612:df3b7a1e883f Fri Nov 04 18:40:00 EDT 2011 Tushar Krishna <tushar@csail.mit.edu> GARNET: adding a fault model for resilient on-chip network research. This patch adds a fault model, which provides the probability of a number of architectural faults in the interconnection network (e.g., data corruption, misrouting). These probabilities can be used to realistically inject faults in GARNET and faithfully evaluate the effectiveness of novel resilient NoC architectures. |
H A D | FaultModel.hh | 8612:df3b7a1e883f Fri Nov 04 18:40:00 EDT 2011 Tushar Krishna <tushar@csail.mit.edu> GARNET: adding a fault model for resilient on-chip network research. This patch adds a fault model, which provides the probability of a number of architectural faults in the interconnection network (e.g., data corruption, misrouting). These probabilities can be used to realistically inject faults in GARNET and faithfully evaluate the effectiveness of novel resilient NoC architectures. |
/gem5/src/mem/ruby/network/ | ||
H A D | BasicRouter.hh | 8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. |
H A D | BasicRouter.py | 8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. |
/gem5/tests/ | ||
H A D | SConscript | 8599:30d0e4c249b5 Sat Oct 22 19:52:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> tests: fix spurious scons "Error 1" messages Turns out these are due to diff reporting that files acutally differed via a non-zero exit code. 8528:1f95c9a0bb2f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add some MP regressions and clean up the disk images and kernels a bit 8498:22a15643e2ca Tue Aug 09 14:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SCons,tests: Tell scons about pc-o3-timing regressions. 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. 8482:353abb676fa2 Tue Aug 02 01:10:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Scons: Drop RUBY as compile time option. This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled. 8397:7cd61d925338 Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> inorder: make InOrder CPU FS compilable/visible make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile 8150:d062791aad69 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Update stats for the previous changes and add ARM_FS/O3 regression. 8120:e4257cde2d79 Fri Mar 04 02:54:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SCons: Turn some scons variables into command line options. 7926:38ade63ef775 Mon Feb 07 04:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add scripts to support X86 FS configurations in the regressions. |
/gem5/src/arch/x86/isa/insts/system/ | ||
H A D | segmentation.py | 8290:3c628a51f6e1 Fri May 06 04:00:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Fix the Lldt instructions so they load the ldtr and not the tr. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | misc.isa | 8550:8ac6c1fa657f Tue Sep 13 01:06:00 EDT 2011 Chander Sudanthi<Chander.Sudanthi@ARM.com> CP15 c15: enable execution with accesses to c15 registers Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented. 8068:749581c26e71 Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Do something for ISB, DSB, DMB 8058:a259ab86cabf Wed Feb 23 16:10:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Adds dummy support for a L2 latency miscreg. 7853:69aae4379062 Tue Jan 18 17:30:00 EST 2011 Matt Horsnell <Matt.Horsnell@ARM.com> ARM: The ARM decoder should not panic when decoding undefined holes is arch. This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. |
/gem5/src/cpu/simple/ | ||
H A D | SConscript | 8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags |
/gem5/src/dev/sparc/ | ||
H A D | mm_disk.cc | 8641:4d3ecac1abec Tue Dec 13 14:49:00 EST 2011 Nathan Binkert <nate@binkert.org> gcc: fix unused variable warnings from GCC 4.6.1 8623:8c410e1a551e Mon Nov 28 04:34:00 EST 2011 Andreas Hansson <andreas.hansson@arm.com> SPARC: Fixing a minor copy-paste bug using the wrong variable There was a bug in the mm_disk implementation where a copy paste error resulted in the d32 variable not being initialised (as it incorrectly was used instead of d16), and gcc 4.5 complaining. 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes |
/gem5/src/dev/x86/ | ||
H A D | i8237.cc | 7903:7fcfb515d7bf Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Add checkpointing capability to devices Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices |
/gem5/src/arch/x86/ | ||
H A D | nativetrace.cc | 8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help 8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes 8107:2e269d6fb3e6 Wed Mar 02 03:41:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Use the npc as the pc when doing a nativetrace, not what M5 considers the pc. 7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
/gem5/src/python/m5/util/ | ||
H A D | terminal.py | 7816:b5003ac75977 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: show sources and targets when building, and colorize output. I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story. |
H A D | sorteddict.py | 8223:394cb2dc3f7c Fri Apr 15 13:38:00 EDT 2011 Nathan Binkert <nate@binkert.org> SortedDict: add functions for getting ranges of keys, values, items |
H A D | grammar.py | 8452:3f2c329e9046 Tue Jul 05 21:30:00 EDT 2011 Nathan Binkert <nate@binkert.org> grammar: better encapsulation of a grammar and parsing This makes it possible to use the grammar multiple times and use the multiple instances concurrently. This makes implementing an include statement as part of a grammar possible. |
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