16365Sgblack@eecs.umich.edu/* 26365Sgblack@eecs.umich.edu * Copyright (c) 2007-2009 The Regents of The University of Michigan 36365Sgblack@eecs.umich.edu * All rights reserved. 46365Sgblack@eecs.umich.edu * 56365Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66365Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76365Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86365Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96365Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106365Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116365Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126365Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136365Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146365Sgblack@eecs.umich.edu * this software without specific prior written permission. 156365Sgblack@eecs.umich.edu * 166365Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176365Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186365Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196365Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206365Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216365Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226365Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236365Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246365Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256365Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266365Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276365Sgblack@eecs.umich.edu * 286365Sgblack@eecs.umich.edu * Authors: Gabe Black 296365Sgblack@eecs.umich.edu */ 306365Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "arch/x86/nativetrace.hh" 3211793Sbrandon.potter@amd.com 3311793Sbrandon.potter@amd.com#include "arch/x86/isa_traits.hh" 348229Snate@binkert.org#include "arch/x86/regs/float.hh" 358229Snate@binkert.org#include "arch/x86/regs/int.hh" 366365Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 378232Snate@binkert.org#include "debug/ExecRegDelta.hh" 386365Sgblack@eecs.umich.edu#include "params/X86NativeTrace.hh" 397678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 406365Sgblack@eecs.umich.edu 416365Sgblack@eecs.umich.edunamespace Trace { 426365Sgblack@eecs.umich.edu 436365Sgblack@eecs.umich.eduvoid 446365Sgblack@eecs.umich.eduX86NativeTrace::ThreadState::update(NativeTrace *parent) 456365Sgblack@eecs.umich.edu{ 466365Sgblack@eecs.umich.edu parent->read(this, sizeof(*this)); 476365Sgblack@eecs.umich.edu rax = X86ISA::gtoh(rax); 486365Sgblack@eecs.umich.edu rcx = X86ISA::gtoh(rcx); 496365Sgblack@eecs.umich.edu rdx = X86ISA::gtoh(rdx); 506365Sgblack@eecs.umich.edu rbx = X86ISA::gtoh(rbx); 516365Sgblack@eecs.umich.edu rsp = X86ISA::gtoh(rsp); 526365Sgblack@eecs.umich.edu rbp = X86ISA::gtoh(rbp); 536365Sgblack@eecs.umich.edu rsi = X86ISA::gtoh(rsi); 546365Sgblack@eecs.umich.edu rdi = X86ISA::gtoh(rdi); 556365Sgblack@eecs.umich.edu r8 = X86ISA::gtoh(r8); 566365Sgblack@eecs.umich.edu r9 = X86ISA::gtoh(r9); 576365Sgblack@eecs.umich.edu r10 = X86ISA::gtoh(r10); 586365Sgblack@eecs.umich.edu r11 = X86ISA::gtoh(r11); 596365Sgblack@eecs.umich.edu r12 = X86ISA::gtoh(r12); 606365Sgblack@eecs.umich.edu r13 = X86ISA::gtoh(r13); 616365Sgblack@eecs.umich.edu r14 = X86ISA::gtoh(r14); 626365Sgblack@eecs.umich.edu r15 = X86ISA::gtoh(r15); 636365Sgblack@eecs.umich.edu rip = X86ISA::gtoh(rip); 646365Sgblack@eecs.umich.edu //This should be expanded if x87 registers are considered 656365Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) 666365Sgblack@eecs.umich.edu mmx[i] = X86ISA::gtoh(mmx[i]); 676365Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++) 686365Sgblack@eecs.umich.edu xmm[i] = X86ISA::gtoh(xmm[i]); 696365Sgblack@eecs.umich.edu} 706365Sgblack@eecs.umich.edu 716365Sgblack@eecs.umich.eduvoid 726365Sgblack@eecs.umich.eduX86NativeTrace::ThreadState::update(ThreadContext *tc) 736365Sgblack@eecs.umich.edu{ 746365Sgblack@eecs.umich.edu rax = tc->readIntReg(X86ISA::INTREG_RAX); 756365Sgblack@eecs.umich.edu rcx = tc->readIntReg(X86ISA::INTREG_RCX); 766365Sgblack@eecs.umich.edu rdx = tc->readIntReg(X86ISA::INTREG_RDX); 776365Sgblack@eecs.umich.edu rbx = tc->readIntReg(X86ISA::INTREG_RBX); 786365Sgblack@eecs.umich.edu rsp = tc->readIntReg(X86ISA::INTREG_RSP); 796365Sgblack@eecs.umich.edu rbp = tc->readIntReg(X86ISA::INTREG_RBP); 806365Sgblack@eecs.umich.edu rsi = tc->readIntReg(X86ISA::INTREG_RSI); 816365Sgblack@eecs.umich.edu rdi = tc->readIntReg(X86ISA::INTREG_RDI); 826365Sgblack@eecs.umich.edu r8 = tc->readIntReg(X86ISA::INTREG_R8); 836365Sgblack@eecs.umich.edu r9 = tc->readIntReg(X86ISA::INTREG_R9); 846365Sgblack@eecs.umich.edu r10 = tc->readIntReg(X86ISA::INTREG_R10); 856365Sgblack@eecs.umich.edu r11 = tc->readIntReg(X86ISA::INTREG_R11); 866365Sgblack@eecs.umich.edu r12 = tc->readIntReg(X86ISA::INTREG_R12); 876365Sgblack@eecs.umich.edu r13 = tc->readIntReg(X86ISA::INTREG_R13); 886365Sgblack@eecs.umich.edu r14 = tc->readIntReg(X86ISA::INTREG_R14); 896365Sgblack@eecs.umich.edu r15 = tc->readIntReg(X86ISA::INTREG_R15); 908107Sgblack@eecs.umich.edu rip = tc->pcState().npc(); 916365Sgblack@eecs.umich.edu //This should be expanded if x87 registers are considered 926365Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) 9313611Sgabeblack@google.com mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i)); 946365Sgblack@eecs.umich.edu for (int i = 0; i < 32; i++) 9513611Sgabeblack@google.com xmm[i] = tc->readFloatReg(X86ISA::FLOATREG_XMM_BASE + i); 966365Sgblack@eecs.umich.edu} 976365Sgblack@eecs.umich.edu 986365Sgblack@eecs.umich.edu 996365Sgblack@eecs.umich.eduX86NativeTrace::X86NativeTrace(const Params *p) 1006365Sgblack@eecs.umich.edu : NativeTrace(p) 1016365Sgblack@eecs.umich.edu{ 1026365Sgblack@eecs.umich.edu checkRcx = true; 1036365Sgblack@eecs.umich.edu checkR11 = true; 1046365Sgblack@eecs.umich.edu} 1056365Sgblack@eecs.umich.edu 1066365Sgblack@eecs.umich.edubool 1076365Sgblack@eecs.umich.eduX86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal) 1086365Sgblack@eecs.umich.edu{ 10911321Ssteve.reinhardt@amd.com if (!checkRcx) 1106365Sgblack@eecs.umich.edu checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal); 11111321Ssteve.reinhardt@amd.com if (checkRcx) 1126365Sgblack@eecs.umich.edu return checkReg(name, mVal, nVal); 1136365Sgblack@eecs.umich.edu return true; 1146365Sgblack@eecs.umich.edu} 1156365Sgblack@eecs.umich.edu 1166365Sgblack@eecs.umich.edubool 1176365Sgblack@eecs.umich.eduX86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal) 1186365Sgblack@eecs.umich.edu{ 11911321Ssteve.reinhardt@amd.com if (!checkR11) 1206365Sgblack@eecs.umich.edu checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val); 12111321Ssteve.reinhardt@amd.com if (checkR11) 1226365Sgblack@eecs.umich.edu return checkReg(name, mVal, nVal); 1236365Sgblack@eecs.umich.edu return true; 1246365Sgblack@eecs.umich.edu} 1256365Sgblack@eecs.umich.edu 1266365Sgblack@eecs.umich.edubool 1276365Sgblack@eecs.umich.eduX86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]) 1286365Sgblack@eecs.umich.edu{ 1296365Sgblack@eecs.umich.edu if (mXmmBuf[num * 2] != nXmmBuf[num * 2] || 1306365Sgblack@eecs.umich.edu mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) { 1316365Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, 1326365Sgblack@eecs.umich.edu "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n", 1336365Sgblack@eecs.umich.edu num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2], 1346365Sgblack@eecs.umich.edu mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]); 1356365Sgblack@eecs.umich.edu return false; 1366365Sgblack@eecs.umich.edu } 1376365Sgblack@eecs.umich.edu return true; 1386365Sgblack@eecs.umich.edu} 1396365Sgblack@eecs.umich.edu 1406365Sgblack@eecs.umich.eduvoid 1416365Sgblack@eecs.umich.eduX86NativeTrace::check(NativeTraceRecord *record) 1426365Sgblack@eecs.umich.edu{ 1436365Sgblack@eecs.umich.edu nState.update(this); 1446365Sgblack@eecs.umich.edu mState.update(record->getThread()); 1456365Sgblack@eecs.umich.edu 14611321Ssteve.reinhardt@amd.com if (record->getStaticInst()->isSyscall()) 1476365Sgblack@eecs.umich.edu { 1486365Sgblack@eecs.umich.edu checkRcx = false; 1496365Sgblack@eecs.umich.edu checkR11 = false; 1506365Sgblack@eecs.umich.edu oldRcxVal = mState.rcx; 1516365Sgblack@eecs.umich.edu oldRealRcxVal = nState.rcx; 1526365Sgblack@eecs.umich.edu oldR11Val = mState.r11; 1536365Sgblack@eecs.umich.edu oldRealR11Val = nState.r11; 1546365Sgblack@eecs.umich.edu } 1556365Sgblack@eecs.umich.edu 1566365Sgblack@eecs.umich.edu checkReg("rax", mState.rax, nState.rax); 1576365Sgblack@eecs.umich.edu checkRcxReg("rcx", mState.rcx, nState.rcx); 1586365Sgblack@eecs.umich.edu checkReg("rdx", mState.rdx, nState.rdx); 1596365Sgblack@eecs.umich.edu checkReg("rbx", mState.rbx, nState.rbx); 1606365Sgblack@eecs.umich.edu checkReg("rsp", mState.rsp, nState.rsp); 1616365Sgblack@eecs.umich.edu checkReg("rbp", mState.rbp, nState.rbp); 1626365Sgblack@eecs.umich.edu checkReg("rsi", mState.rsi, nState.rsi); 1636365Sgblack@eecs.umich.edu checkReg("rdi", mState.rdi, nState.rdi); 1646365Sgblack@eecs.umich.edu checkReg("r8", mState.r8, nState.r8); 1656365Sgblack@eecs.umich.edu checkReg("r9", mState.r9, nState.r9); 1666365Sgblack@eecs.umich.edu checkReg("r10", mState.r10, nState.r10); 1676365Sgblack@eecs.umich.edu checkR11Reg("r11", mState.r11, nState.r11); 1686365Sgblack@eecs.umich.edu checkReg("r12", mState.r12, nState.r12); 1696365Sgblack@eecs.umich.edu checkReg("r13", mState.r13, nState.r13); 1706365Sgblack@eecs.umich.edu checkReg("r14", mState.r14, nState.r14); 1716365Sgblack@eecs.umich.edu checkReg("r15", mState.r15, nState.r15); 1726365Sgblack@eecs.umich.edu checkReg("rip", mState.rip, nState.rip); 1736365Sgblack@eecs.umich.edu checkXMM(0, mState.xmm, nState.xmm); 1746365Sgblack@eecs.umich.edu checkXMM(1, mState.xmm, nState.xmm); 1756365Sgblack@eecs.umich.edu checkXMM(2, mState.xmm, nState.xmm); 1766365Sgblack@eecs.umich.edu checkXMM(3, mState.xmm, nState.xmm); 1776365Sgblack@eecs.umich.edu checkXMM(4, mState.xmm, nState.xmm); 1786365Sgblack@eecs.umich.edu checkXMM(5, mState.xmm, nState.xmm); 1796365Sgblack@eecs.umich.edu checkXMM(6, mState.xmm, nState.xmm); 1806365Sgblack@eecs.umich.edu checkXMM(7, mState.xmm, nState.xmm); 1816365Sgblack@eecs.umich.edu checkXMM(8, mState.xmm, nState.xmm); 1826365Sgblack@eecs.umich.edu checkXMM(9, mState.xmm, nState.xmm); 1836365Sgblack@eecs.umich.edu checkXMM(10, mState.xmm, nState.xmm); 1846365Sgblack@eecs.umich.edu checkXMM(11, mState.xmm, nState.xmm); 1856365Sgblack@eecs.umich.edu checkXMM(12, mState.xmm, nState.xmm); 1866365Sgblack@eecs.umich.edu checkXMM(13, mState.xmm, nState.xmm); 1876365Sgblack@eecs.umich.edu checkXMM(14, mState.xmm, nState.xmm); 1886365Sgblack@eecs.umich.edu checkXMM(15, mState.xmm, nState.xmm); 1896365Sgblack@eecs.umich.edu} 1906365Sgblack@eecs.umich.edu 1917811Ssteve.reinhardt@amd.com} // namespace Trace 1926365Sgblack@eecs.umich.edu 1936365Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 1946365Sgblack@eecs.umich.edu// 1956365Sgblack@eecs.umich.edu// ExeTracer Simulation Object 1966365Sgblack@eecs.umich.edu// 1976365Sgblack@eecs.umich.eduTrace::X86NativeTrace * 1986365Sgblack@eecs.umich.eduX86NativeTraceParams::create() 1996365Sgblack@eecs.umich.edu{ 2006365Sgblack@eecs.umich.edu return new Trace::X86NativeTrace(this); 2018902Sandreas.hansson@arm.com} 202